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[209.132.180.67]) by mx.google.com with ESMTP id x1-v6si9492395plb.523.2018.03.05.06.52.56; Mon, 05 Mar 2018 06:53:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=OLgEu9cR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932482AbeCEOvf (ORCPT + 99 others); Mon, 5 Mar 2018 09:51:35 -0500 Received: from mail-it0-f68.google.com ([209.85.214.68]:52139 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751495AbeCEOva (ORCPT ); Mon, 5 Mar 2018 09:51:30 -0500 Received: by mail-it0-f68.google.com with SMTP id u66so9710629ith.1 for ; Mon, 05 Mar 2018 06:51:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=wDhyNvvZP2AiwUiw4igZ2Spz8pQgeLknHc4+VcmYO48=; b=OLgEu9cR01UiLHb0v86tJCTqGgVGvEDyehkxeUDFfL4NEm4XftlQqlW3oHFxCoX1LZ ZANGxvuAxSQ52plgvoyeek5i/8bEid0NfcsgjiqTxGwVZ1GKJDWBPdjaBvBxLWLN57K6 oGNh/ImoXd3kBH9t8vlGNs+ynyaeODJBrkH4+OG08KHKGAKoJ0gVjrLByatXs89wiq0N xy7g74BvX9l0klUbUJHYKlPmryK1ykLwh66rj/+nbXbdr1l68DBPeehRUUPo/vVNG/kj Sc/QLjkerJy0DTJUm+sqNPvg/mAYMhmC3eBnU+zNxclIbm15uQo1GoFseQjV2JzDnVF6 YfOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=wDhyNvvZP2AiwUiw4igZ2Spz8pQgeLknHc4+VcmYO48=; b=CXbbbMu3n/qx3jn9DRk0IlfxGPHWMd/iMtR5IlF9bL7vEPwaKw+ywXWweVak55lksW bp8PDqqEvPfe5MQAqwvN/53AmnPP3bSRYbQo0VEeSgxvlAj7SSX2SIK7BLL4mQ4EeMNw 0IDl2oizMMB4hFj5rCiz6+1s5204EGGeZ/XZ+w0BlSvKSEL1BKJQFvu1tkQ7U32/gFiK nY3kTve+ZfmMmlq3w+f4wfEEikrNb7U828JNrrWTfbGyq/BKYaQ1tN37XZtfnk7k/V5j unvHksAR8Mm/DrXNlamaaSu/YH6zla55odLCw7xuSA58+ON1R8QfQD4HEiIEhB2d9UIy FDUQ== X-Gm-Message-State: AElRT7FCOtIxye1ZzSEpeX/qoeJZdCZZJjACQ7+Ku2uKaOT1gmIxswoh Nlh0QUuymV/eRx4mtwjfIMEhWxr6DUsuTaGgwA== X-Received: by 10.36.208.4 with SMTP id m4mr15109084itg.69.1520261489763; Mon, 05 Mar 2018 06:51:29 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.118.212 with HTTP; Mon, 5 Mar 2018 06:51:29 -0800 (PST) In-Reply-To: <20180305131231.GR16484@8bytes.org> References: <1520245563-8444-1-git-send-email-joro@8bytes.org> <1520245563-8444-8-git-send-email-joro@8bytes.org> <20180305131231.GR16484@8bytes.org> From: Brian Gerst Date: Mon, 5 Mar 2018 09:51:29 -0500 Message-ID: Subject: Re: [PATCH 07/34] x86/entry/32: Restore segments before int registers To: Joerg Roedel Cc: Linus Torvalds , Thomas Gleixner , Ingo Molnar , Peter Anvin , "the arch/x86 maintainers" , Linux Kernel Mailing List , linux-mm , Andrew Lutomirski , Dave Hansen , Josh Poimboeuf , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , David Laight , Denys Vlasenko , Eduardo Valentin , Greg Kroah-Hartman , Will Deacon , "Liguori, Anthony" , Daniel Gruss , Hugh Dickins , Kees Cook , Andrea Arcangeli , Waiman Long , Pavel Machek , Joerg Roedel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 5, 2018 at 8:12 AM, Joerg Roedel wrote: > On Mon, Mar 05, 2018 at 04:17:45AM -0800, Linus Torvalds wrote: >> Restoring the segments can cause exceptions that need to be >> handled. With PTI enabled, we still need to be on kernel cr3 >> when the exception happens. For the cr3-switch we need >> at least one integer scratch register, so we can't switch >> with the user integer registers already loaded. >> >> >> This fundamentally seems wrong. > > Okay, right, with v3 it is wrong, in v2 I still thought I could get away > without remembering the entry-cr3, but didn't think about the #DB case > then. > > In v3 I added code which remembers the entry-cr3 and handles the > entry-from-kernel-mode-with-user-cr3 case for all exceptions including > #DB. > >> The things is, we *know* that we will restore two segment registers with the >> user cr3 already loaded: CS and SS get restored with the final iret. > > Yeah, I know, but the iret-exception path is fine because it will > deliver a SIGILL and doesn't return to the faulting iret. > > Anyway, I will remove these restore-reorderings, they are not needed > anymore. > >> So has this been tested with >> >> - single-stepping through sysenter >> >> This takes a DB fault in the first kernel instruction. We're in kernel mode, >> but with user cr3. >> >> - ptracing and setting CS/SS to something bad >> >> That should test the "exception on iret" case - again in kernel mode, but >> with user cr3 restored for the return. > > The iret-exception case is tested by the ldt_gdt selftest (the > do_multicpu_tests subtest). But I didn't actually tested single-stepping > through sysenter yet. I just re-ran the same tests I did with v2 on this > patch-set. > > Regards, > > Joerg > For the IRET fault case you will still need to catch it in the exception code. See the 64-bit code (.Lerror_bad_iret) for example. For 32-bit, you could just expand that check to cover the whole exit prologue after the CR3 switch, including the data segment loads. I do wonder though, how expensive is a CR3 read? The SDM implies that only writes are serializing. It may be simpler to just unconditionally check it. -- Brian Gerst