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[209.132.180.67]) by mx.google.com with ESMTP id k1-v6si9839100pli.616.2018.03.05.09.22.52; Mon, 05 Mar 2018 09:23:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=p4gox/sV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752700AbeCERVj (ORCPT + 99 others); Mon, 5 Mar 2018 12:21:39 -0500 Received: from mail-it0-f66.google.com ([209.85.214.66]:34872 "EHLO mail-it0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751462AbeCERVi (ORCPT ); Mon, 5 Mar 2018 12:21:38 -0500 Received: by mail-it0-f66.google.com with SMTP id v194so11038503itb.0 for ; Mon, 05 Mar 2018 09:21:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=mrp+Wh0z2gT/Zi88cP7fAjz8VKTEMszGmyl9+rEPY/Y=; b=p4gox/sVhkJ1stLkmbXwcV5+g7PQ7/yTljEaVv6PtgbKvsgPLpp7eSeIRV9SPBV9k+ 02wGbhDy9uYdcAy15bhZAAqRgTgyQEpgbRp4pgrBnJ3zG8mGGNtyG3DwFWeJJRBds3YJ 0PzzLke1GgySBKBFQmYoyAUUR2dSzHOK5BdKbX4LUfXjsYIO4guAwsYMqpjqRRKp7sqg ng/5Jwoe150joQ2Ru2KsZo+JXyAnG1iplNv6c8GX9GtiJoHsy4SmNELR6P2hyR0ipzBS bfwPVUn7SVWyU1l30PE0v/VCaoAx2zRorMpLaMBqq2kMpblC+YYYTWjw+LcWGMvBOVEd Ehvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=mrp+Wh0z2gT/Zi88cP7fAjz8VKTEMszGmyl9+rEPY/Y=; b=pb5ar4qhveBfGapisO3NXMeJgd3BLid5Wn+NIe+0nC4371cxKeRJIVWCtqdBiVsfyJ mKbjYDBQNIs/m5kCVzBrPYWDlaQQ6r0n1f483reS1nXgQkXZqWu/FptOsVrk+8wpiF4g CmLSp7YT/Ha/FCtHYJu/WH5cBRcNQ7IR1C0rzLMDNX6GrEZqUg7k+mnTE4NvSJag6bdf J9J9KW677IGTsUwpomnlDkVQucV2mKa9U+BqnVm9rhgyKUdnS6xlqUW8HmGQcZAtNleQ WuGzu/dCFDQLUiQGVhhP9J8JTKg8M+qBH5I7oYC7YGNurExCADuUbKzFWt9dCXn/nbxU S0cg== X-Gm-Message-State: AElRT7H2kYLE/+TR8T1pD3PvwCSLCtUw7vFXQQvkeMR2Sl1unfWnRxnY u8af0J5LzBAfwDtOoxti6O6tzpB0MjCdcwe0jw== X-Received: by 10.36.178.77 with SMTP id h13mr14850726iti.2.1520270497419; Mon, 05 Mar 2018 09:21:37 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.118.212 with HTTP; Mon, 5 Mar 2018 09:21:36 -0800 (PST) In-Reply-To: <20180305164448.GS16484@8bytes.org> References: <1520245563-8444-1-git-send-email-joro@8bytes.org> <1520245563-8444-8-git-send-email-joro@8bytes.org> <20180305131231.GR16484@8bytes.org> <20180305164448.GS16484@8bytes.org> From: Brian Gerst Date: Mon, 5 Mar 2018 12:21:36 -0500 Message-ID: Subject: Re: [PATCH 07/34] x86/entry/32: Restore segments before int registers To: Joerg Roedel Cc: Linus Torvalds , Thomas Gleixner , Ingo Molnar , Peter Anvin , "the arch/x86 maintainers" , Linux Kernel Mailing List , linux-mm , Andrew Lutomirski , Dave Hansen , Josh Poimboeuf , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , David Laight , Denys Vlasenko , Eduardo Valentin , Greg Kroah-Hartman , Will Deacon , "Liguori, Anthony" , Daniel Gruss , Hugh Dickins , Kees Cook , Andrea Arcangeli , Waiman Long , Pavel Machek , Joerg Roedel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 5, 2018 at 11:44 AM, Joerg Roedel wrote: > On Mon, Mar 05, 2018 at 09:51:29AM -0500, Brian Gerst wrote: >> For the IRET fault case you will still need to catch it in the >> exception code. See the 64-bit code (.Lerror_bad_iret) for example. >> For 32-bit, you could just expand that check to cover the whole exit >> prologue after the CR3 switch, including the data segment loads. > > I had a look at the 64 bit code and the exception-in-kernel case seems > to be handled differently than on 32 bit. The 64 bit entry code has > checks for certain kinds of errors like iret exceptions. > > On 32 bit this is implemented via the standard exception tables which > get an entry for every EIP that might fault (usually segment loading > operations, but also iret). > > So, unless I am missing something, all the exception entry code has to > do is to remember the stack and the cr3 with which it was entered (if > entered from kernel mode) and restore those before iret. And this is > what I implemented in v3 of this patch-set. I also noticed that 32-bit will raise SIGILL for all IRET faults, while 64-bit will raise SIGBUS (#NP/#SS) or SIGSEGV (#GP). The 64-bit code is better since it doesn't lose the original fault type, whereas SIGILL is wrong for this case (illegal opcode). -- Brian Gerst