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[216.188.254.6]) by smtp.gmail.com with ESMTPSA id u70sm7595509ota.81.2018.03.05.17.51.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Mar 2018 17:51:03 -0800 (PST) Date: Mon, 5 Mar 2018 19:51:02 -0600 From: Rob Herring To: sean.wang@mediatek.com Cc: sboyd@codeaurora.org, mturquette@baylibre.com, matthias.bgg@gmail.com, mark.rutland@arm.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 1/2] dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4 Message-ID: <20180306015102.alzc5a7sxmtbphzz@rob-hp-laptop> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 01, 2018 at 11:27:50AM +0800, sean.wang@mediatek.com wrote: > From: Sean Wang > > Just add binding for a fixed-factor clock axisel_d4, which would be > referenced by PWM devices on MT7623 or MT2701 SoC. > > Cc: stable@vger.kernel.org > Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks") > Signed-off-by: Sean Wang > Cc: Rob Herring > Cc: Mark Rutland > Cc: devicetree@vger.kernel.org > --- > include/dt-bindings/clock/mt2701-clk.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Rob Herring