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[209.132.180.67]) by mx.google.com with ESMTP id e93-v6si10631546plk.159.2018.03.05.23.38.25; Mon, 05 Mar 2018 23:38:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@ffwll.ch header.s=google header.b=WK1TCwl6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750939AbeCFHhP (ORCPT + 99 others); Tue, 6 Mar 2018 02:37:15 -0500 Received: from mail-wm0-f41.google.com ([74.125.82.41]:55459 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750730AbeCFHhN (ORCPT ); Tue, 6 Mar 2018 02:37:13 -0500 Received: by mail-wm0-f41.google.com with SMTP id q83so20789847wme.5 for ; Mon, 05 Mar 2018 23:37:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=sender:date:from:to:cc:subject:message-id:mail-followup-to :references:mime-version:content-disposition :content-transfer-encoding:in-reply-to:user-agent; bh=0Yc4qE608R+3TyMcU/GapOB+SSMilFXe8sTXs1vgCaA=; b=WK1TCwl6H662n7z1P11LEGiFWhsOBQS61PtOs3FmmrCkC+RD1wLyj1Qfyel6Q0ZhKS tDUI9fCd9pJ/3nngC7ltGf7yc5ISnGZxA1dsIy7FOBYabYR1TqhWFMJBK3ICLG4+mtrS qUB4MHIEcT04sJNZRhkk4p4fpl0f10lcMVnko= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :content-transfer-encoding:in-reply-to:user-agent; bh=0Yc4qE608R+3TyMcU/GapOB+SSMilFXe8sTXs1vgCaA=; b=GvmxmzG/9YDltKVmrZvX9mPewXv/vRQkShaMoxekSehXNP2wvvbfXjTPx1rwcp4cOu 1Zs3PSUq9qKSOJbCWEKBp6YBOcxE4fyYR4NnJBgUKNyFbdcqSAXRRZ530xPhketgQplc q5/B3BLu2L6YyNp9KUfvmPkvcZlHYV2PnSMrXVwjbdcrq3nLsQvuzPnsg15LLiqUOgCj cntQ6zvD5Iy6BYlPhjVEcrw7e/fGpgzR1ilDF4K6DgJDIStpIZ5tvXRqcuLtjoZbJHmm IiK1EoBrU63S27aaoKG+uDv/O4Uxf9Q/kyKGBE6qH00lk63NzTjJiWOga5y5o0D0ECts eQfA== X-Gm-Message-State: AElRT7E4fiHSP1S1A3ZM+atBKb8zPmS91viT9/NhkbnV3m2sf7Qet6Mf 4xNI8xheOmEQftbHFn5H/rWS6w== X-Received: by 10.80.131.198 with SMTP id 64mr5043874edi.273.1520321831939; Mon, 05 Mar 2018 23:37:11 -0800 (PST) Received: from phenom.ffwll.local ([2a02:168:5635:0:39d2:f87e:2033:9f6]) by smtp.gmail.com with ESMTPSA id c22sm15053620eda.1.2018.03.05.23.37.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Mar 2018 23:37:11 -0800 (PST) Date: Tue, 6 Mar 2018 08:37:09 +0100 From: Daniel Vetter To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Rob Clark , David Airlie , linux-arm-msm , Linux Kernel Mailing List , dri-devel Subject: Re: [PATCH 1/4] drm/atomic: integrate modeset lock with private objects Message-ID: <20180306073709.GT22212@phenom.ffwll.local> Mail-Followup-To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Rob Clark , David Airlie , linux-arm-msm , Linux Kernel Mailing List , dri-devel References: <20180221143730.30285-2-robdclark@gmail.com> <20180221144919.GN5453@intel.com> <20180221150727.GO5453@intel.com> <20180221152720.GP5453@intel.com> <20180221155410.GQ5453@intel.com> <20180221163654.GS5453@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20180221163654.GS5453@intel.com> X-Operating-System: Linux phenom 4.14.0-3-amd64 User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 21, 2018 at 06:36:54PM +0200, Ville Syrj?l? wrote: > On Wed, Feb 21, 2018 at 11:17:21AM -0500, Rob Clark wrote: > > On Wed, Feb 21, 2018 at 10:54 AM, Ville Syrj?l? > > wrote: > > > On Wed, Feb 21, 2018 at 10:36:06AM -0500, Rob Clark wrote: > > >> On Wed, Feb 21, 2018 at 10:27 AM, Ville Syrj?l? > > >> wrote: > > >> > On Wed, Feb 21, 2018 at 10:20:03AM -0500, Rob Clark wrote: > > >> >> On Wed, Feb 21, 2018 at 10:07 AM, Ville Syrj?l? > > >> >> wrote: > > >> >> > On Wed, Feb 21, 2018 at 09:54:49AM -0500, Rob Clark wrote: > > >> >> >> On Wed, Feb 21, 2018 at 9:49 AM, Ville Syrj?l? > > >> >> >> wrote: > > >> >> >> > On Wed, Feb 21, 2018 at 09:37:21AM -0500, Rob Clark wrote: > > >> >> >> >> Follow the same pattern of locking as with other state objects. This > > >> >> >> >> avoids boilerplate in the driver. > > >> >> >> > > > >> >> >> > I'm not sure we really want to do this. What if the driver wants a > > >> >> >> > custom locking scheme for this state? > > >> >> >> > > >> >> >> That seems like something we want to discourage, ie. all the more > > >> >> >> reason for this patch. > > >> >> >> > > >> >> >> There is no reason drivers could not split their global state into > > >> >> >> multiple private objs's, each with their own lock, for more fine > > >> >> >> grained locking. That is basically the only valid reason I can think > > >> >> >> of for "custom locking". > > >> >> > > > >> >> > In i915 we have at least one case that would want something close to an > > >> >> > rwlock. Any crtc lock is enough for read, need all of them for write. > > >> >> > Though if we wanted to use private objs for that we might need to > > >> >> > actually make the states refcounted as well, otherwise I can imagine > > >> >> > we might land in some use-after-free issues once again. > > >> >> > > > >> >> > Maybe we could duplicate the state into per-crtc and global copies, but > > >> >> > then we have to keep all of those in sync somehow which doesn't sound > > >> >> > particularly pleasant. > > >> >> > > >> >> Or just keep your own driver lock for read, and use that plus the core > > >> >> modeset lock for write? > > >> > > > >> > If we can't add the private obj to the state we can't really use it. > > >> > > > >> > > >> I'm not sure why that is strictly true (that you need to add it to the > > >> state if for read-only), since you'd be guarding it with your own > > >> driver read-lock you can just priv->foo_state->bar. > > >> > > >> Since it is read-only access, there is no roll-back to worry about for > > >> test-only or failed atomic_check()s.. > > > > > > That would be super ugly. We want to access the information the same > > > way whether it has been modified or not. > > > > Well, I mean the whole idea of what you want to do seems a bit super-ugly ;-) > > > > I mean, in mdp5 the assigned global resources go in plane/crtc state, > > and tracking of what is assigned to which plane/crtc is in global > > state, so it fits nicely in the current locking model. For i915, I'm > > not quite sure what is the global state you are concerned about, so it > > is a bit hard to talk about the best solution in the abstract. Maybe > > the better option is to teach modeset-lock how to be a rwlock instead? > > The thing I'm thinking is the core display clock (cdclk) frequency which > we need to consult whenever computing plane states and whatnot. We don't > want a modeset on one crtc to block a plane update on another crtc > unless we actually have to bump the cdclk (which would generally require > all crtcs to undergo a full modeset). Seems like a generally useful > pattern to me. The usual way to fix that is to have read-only copies of the state in the plane or crtc states. And for writing (or if the requirement changes) you have to lock all the objects. Essentially what Rob's doing for his plane/crtc assignment stuff. What we do in i915 is kinda not what I've been recommending to everyone else, because it is a rather tricky and complicated way to get things done. Sure there's a tradeoff between duplicating data and complicated locking schemes, but I think for the kms case having to explicitly type code that reflects the depencies in computation (instead of having that embedded implicitly in the locking scheme) is a feature, not a bug. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch