Received: by 10.223.185.116 with SMTP id b49csp3577968wrg; Tue, 6 Mar 2018 01:10:49 -0800 (PST) X-Google-Smtp-Source: AG47ELvqF5evTa/fvvO9DtxQ1NW0b4kf2sW9MIZcQqyaPurDroLPF6AyA0dCrrYiFL8e/8ylnvdY X-Received: by 2002:a17:902:5906:: with SMTP id o6-v6mr15315080pli.60.1520327449484; Tue, 06 Mar 2018 01:10:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520327449; cv=none; d=google.com; s=arc-20160816; b=VuGA48puS3BjTlGAs0BhtAeT3DTABIBy1+blFaL/cng5I8P93WqGlzqkB/UkU17SY9 dhjbVShBNiJYLLAqIVNiWDDJs1u/fOM376rIpU5YNDFfR4Bz2hf/jFKTexWCTp3zXkN5 l7NUBZY1rqOTLX1Fv67S4Nt8U99UqLlF/rGLnbumvRk3T3JnZunhjYTHN8iR8JUGzazE bbkC+0MfuYcXE2zmFLyyJoEMUDZF10R4PmacsoTfmKRSGuue+oOxSatAVmAy2Gsf4k4A 4+fuXY8IDLwxcW0H8rEY55ZbPDxaTcir29JB/0ZKFzKOBYOo9CD4tDRudMnYu//TpJSA EaRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=wmiy85GGom+PCKzIqXxPXuurNfQuwHHBUkEHyCeSSew=; b=hjGtNPmBPfXo9eqZynTJ+HQxNXcbJ6Yqegk0Ftk00ROo0pW6HoWgdAUF3TPX+3Z6IS JHxubN6XNaiGzDdB3tcd6XsagtIeNExwdCtyODUsN+g+9IuhiPQootmRB+azaQUOB9Tx XayDDk8IZVGUkAdeyU7esQX5v5TcEbYG7LRRLhtu4c6KW7YOI8I+I1uBeweWWCCebKRe TZh517rS6kqLgPsIhE3Esm+5In3E9gN3HCtyMUS6WP+4X3wfZFdMfok9u+n1NcQQWU+z 8y++1jl+pwkWnWQ0p3ksGJYW+C1Vdk93yfjSodEco8WUySd0oMLcu9ZK2YdUnw2Sak1L lI7w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l6si9527292pgp.249.2018.03.06.01.10.34; Tue, 06 Mar 2018 01:10:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753065AbeCFJJi (ORCPT + 99 others); Tue, 6 Mar 2018 04:09:38 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:16569 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750817AbeCFJJg (ORCPT ); Tue, 6 Mar 2018 04:09:36 -0500 X-UUID: 1a8ba1155a444dfb97a3f0e157215465-20180306 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1935463996; Tue, 06 Mar 2018 17:09:34 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 6 Mar 2018 17:09:33 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 6 Mar 2018 17:09:33 +0800 From: Ryder Lee To: Stephen Boyd , Rob Herring CC: Mark Brown , Lee Jones , Matthias Brugger , , , , , , Garlic Tseng , Ryder Lee Subject: [PATCH v4 1/6] clk: mediatek: update missing clock data for MT7622 audsys Date: Tue, 6 Mar 2018 17:09:26 +0800 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys. Signed-off-by: Ryder Lee Reviewed-by: Rob Herring Reviewed-by: Matthias Brugger --- drivers/clk/mediatek/clk-mt7622-aud.c | 1 + include/dt-bindings/clock/mt7622-clk.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index fad7d9f..13f752d 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -106,6 +106,7 @@ GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20), GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21), GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22), + GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23), /* AUDIO2 */ GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0), GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1), diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 3e514ed..e9d77f0 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -235,7 +235,8 @@ #define CLK_AUDIO_MEM_ASRC3 43 #define CLK_AUDIO_MEM_ASRC4 44 #define CLK_AUDIO_MEM_ASRC5 45 -#define CLK_AUDIO_NR_CLK 46 +#define CLK_AUDIO_AFE_CONN 46 +#define CLK_AUDIO_NR_CLK 47 /* SSUSBSYS */ -- 1.9.1