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[209.132.180.67]) by mx.google.com with ESMTP id w5-v6si10783061plz.551.2018.03.06.03.47.56; Tue, 06 Mar 2018 03:48:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=synopsys.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753564AbeCFLq3 (ORCPT + 99 others); Tue, 6 Mar 2018 06:46:29 -0500 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:41037 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753539AbeCFLq0 (ORCPT ); Tue, 6 Mar 2018 06:46:26 -0500 Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 3C13510C0368; Tue, 6 Mar 2018 03:46:26 -0800 (PST) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 21D913B73; Tue, 6 Mar 2018 03:46:26 -0800 (PST) Received: from paltsev-e7480.internal.synopsys.com (unknown [10.121.8.67]) by mailhost.synopsys.com (Postfix) with ESMTP id 6E1CC3B5D; Tue, 6 Mar 2018 03:46:23 -0800 (PST) From: Eugeniy Paltsev To: dmaengine@vger.kernel.org Cc: linux-snps-arc@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Vinod Koul , Dan Williams , Rob Herring , Wan Ahmad Zainie , Alexey Brodkin , Andy Shevchenko , Eugeniy Paltsev Subject: [PATCH v3 2/2] dt-bindings: Document the Synopsys DW AXI DMA bindings Date: Tue, 6 Mar 2018 14:46:15 +0300 Message-Id: <20180306114615.8895-3-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180306114615.8895-1-Eugeniy.Paltsev@synopsys.com> References: <20180306114615.8895-1-Eugeniy.Paltsev@synopsys.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds documentation of device tree bindings for the Synopsys DesignWare AXI DMA controller. Signed-off-by: Eugeniy Paltsev --- Changes v2->v3: * None. .../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt new file mode 100644 index 000000000000..f237b7928283 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt @@ -0,0 +1,41 @@ +Synopsys DesignWare AXI DMA Controller + +Required properties: +- compatible: "snps,axi-dma-1.01a" +- reg: Address range of the DMAC registers. This should include + all of the per-channel registers. +- interrupt: Should contain the DMAC interrupt number. +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device. +- dma-channels: Number of channels supported by hardware. +- snps,dma-masters: Number of AXI masters supported by the hardware. +- snps,data-width: Maximum AXI data width supported by hardware. + (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) +- snps,priority: Priority of channel. Array size is equal to the number of + dma-channels. Priority value must be programmed within [0:dma-channels-1] + range. (0 - minimum priority) +- snps,block-size: Maximum block size supported by the controller channel. + Array size is equal to the number of dma-channels. + +Optional properties: +- snps,axi-max-burst-len: Restrict master AXI burst length by value specified + in this property. If this property is missing the maximum AXI burst length + supported by DMAC is used. [1:256] + +Example: + +dmac: dma-controller@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + clocks = <&core_clk>, <&cfgr_clk>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <27>; + + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; +}; -- 2.14.3