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[209.132.180.67]) by mx.google.com with ESMTP id v10-v6si7025013plz.763.2018.03.06.05.46.56; Tue, 06 Mar 2018 05:47:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753654AbeCFNqA (ORCPT + 99 others); Tue, 6 Mar 2018 08:46:00 -0500 Received: from mga07.intel.com ([134.134.136.100]:34632 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750947AbeCFNp6 (ORCPT ); Tue, 6 Mar 2018 08:45:58 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Mar 2018 05:45:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,431,1515484800"; d="scan'208";a="35015544" Received: from mbmacphe-mobl.amr.corp.intel.com (HELO [10.254.80.80]) ([10.254.80.80]) by fmsmga004.fm.intel.com with ESMTP; 06 Mar 2018 05:45:56 -0800 Subject: Re: [PATCH 07/34] x86/entry/32: Restore segments before int registers To: Ingo Molnar , "H. Peter Anvin" References: <1520245563-8444-1-git-send-email-joro@8bytes.org> <1520245563-8444-8-git-send-email-joro@8bytes.org> <20180305131231.GR16484@8bytes.org> <20180305213550.GV16484@8bytes.org> <12c11262-5e0f-2987-0a74-3bde4b66c352@zytor.com> <20180306070437.kf3fkevqj6cuxptz@gmail.com> Cc: Linus Torvalds , Joerg Roedel , Brian Gerst , Thomas Gleixner , the arch/x86 maintainers , Linux Kernel Mailing List , linux-mm , Andrew Lutomirski , Josh Poimboeuf , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , David Laight , Denys Vlasenko , Eduardo Valentin , Greg Kroah-Hartman , Will Deacon , "Liguori, Anthony" , Daniel Gruss , Hugh Dickins , Kees Cook , Andrea Arcangeli , Waiman Long , Pavel Machek , Joerg Roedel From: Dave Hansen Message-ID: <6224cf9e-4c13-58e5-4541-c06074a20191@intel.com> Date: Tue, 6 Mar 2018 05:45:56 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180306070437.kf3fkevqj6cuxptz@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/05/2018 11:04 PM, Ingo Molnar wrote: > * H. Peter Anvin wrote: >> On NX-enabled hardware NX works with PDE, but the PDPDT in general doesn't >> have permission bits (it's really more of a set of four CR3s than a page >> table level.) > The 4 PDPDT entries are also shadowed in the CPU and are only refreshed > on CR3 loads, not spontaneously reloaded from memory during TLB walk > like regular page table entries, right? Yes. The SDM even calls them non-architectural "PDPTE Registers" and talks about them only being loaded at CR3 write time. ~5 years ago we even had a bug directly related to this feature: > https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/?id=324cdc3f7e6a752fe0e95fa7b5c9664171a34ded