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[209.132.180.67]) by mx.google.com with ESMTP id c16-v6si7906158pls.801.2018.03.06.06.31.56; Tue, 06 Mar 2018 06:32:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=DZJ3z5Lw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753784AbeCFOas (ORCPT + 99 others); Tue, 6 Mar 2018 09:30:48 -0500 Received: from mail-qk0-f193.google.com ([209.85.220.193]:39338 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753760AbeCFOar (ORCPT ); Tue, 6 Mar 2018 09:30:47 -0500 Received: by mail-qk0-f193.google.com with SMTP id z197so25042858qkb.6 for ; Tue, 06 Mar 2018 06:30:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=Enk1ZTVyWc3YSmtYriuHVKcw8wqTNhY6wyH5ezRX9l4=; b=DZJ3z5Lwp0VRSm2wUksWd+XWvyVbFhTIU6yGiaNb7ldgZVIFYmnM5q/FF7OfnOW5Go j9R/SO6zYMpFLCbp66Ty3fkO7C/QWZrDmC0RbyUU+EJHm9cFOEExZTfRgye7MWopEEDh 0aCe4+K+FOexCb2pT5qyjgMrJ1LlI8z1nsW44m6ROGGjMijXP5Kp7OFbxgJbDPXuCGc4 etF0tCZP61dkpmHJl4jM8e2d/80POdyzMpChEl4BavZZadpreSUzW/x1UNqOam9KhX4v rD3/kHZ7/3URI/AfcXkbc2pVrMET8wHNR9rlkLsHD9//pke/tyC8vha+xejcgMmCV9Dm vy9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=Enk1ZTVyWc3YSmtYriuHVKcw8wqTNhY6wyH5ezRX9l4=; b=OVad1ut9JG7Ir9GJc5qTooeQdm+UN/jOHAVvf6ySAiXEvWjx5QuqM62nguaEao6sUQ sRPUH/VZwZudMaLD1s6gzXwqTVapGXhiJ0MJZE7tEeD1V+Cey1j9rptRKHa2UBp1U/qz 6jmHUhyMR5gBeiFuvB6i5Y1qew0guHDggLC0hn9tpzOCTNruDQeddP+aYFO3zTYW4kcT /Sr5EvfVrc5SVcW8fFv2ezijt5T0BDX6ZazbcC89PYUL0S1M55pCiInHirYFXvX92Uve ytQwl59Jbsi3zJ2pN8E1iN3567FN8PHF63zbsuTW2/6WXoGqofS3WbFc7TRtdmofQ0pN a7Xw== X-Gm-Message-State: AElRT7EAC8ozRsZBkAMv4nch0IZ3PbFBi2RcL8c9SFwN6g8ZUJKhgpbV I2TnpaLx0NPypMOt8VRcCnOBQVQdvXzI3IIDKtk= X-Received: by 10.55.215.153 with SMTP id t25mr26494151qkt.343.1520346646400; Tue, 06 Mar 2018 06:30:46 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.185.46 with HTTP; Tue, 6 Mar 2018 06:30:45 -0800 (PST) In-Reply-To: <20180306140201.GB7428@hc> References: <20180302143737.10788-1-jglauber@cavium.com> <20180302143737.10788-2-jglauber@cavium.com> <20180306140201.GB7428@hc> From: Arnd Bergmann Date: Tue, 6 Mar 2018 15:30:45 +0100 X-Google-Sender-Auth: 1DIB0zH2kWMjewLoRgk7qOh-SOw Message-ID: Subject: Re: [PATCH 2/2] arm64: defconfig: Raise NR_CPUS to 256 To: Jan Glauber Cc: Catalin Marinas , Will Deacon , Linux ARM , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 6, 2018 at 3:02 PM, Jan Glauber wrote: > On Tue, Mar 06, 2018 at 02:12:29PM +0100, Arnd Bergmann wrote: >> On Fri, Mar 2, 2018 at 3:37 PM, Jan Glauber wrote: >> > ThunderX1 dual socket has 96 CPUs and ThunderX2 has 224 CPUs. >> >> Are you sure about those numbers? From my counting, I would have expected >> twice that number in both cases: 48 cores, 2 chips and 2x SMT for ThunderX >> vs 52 Cores, 2 chips and 4x SMT for ThunderX2. > > That's what I have on those machines. I counted SMT as normal CPUs as it > doesn't make a difference for the config. I've not seen SMT on ThunderX. > > The ThunderX2 number of 224 is already with 4x SMT (and 2 chips) but > there may be other versions planned that I'm not aware of. I've never used on, the numbers I have are probably the highest announced core counts that are produced, but it's possible that those with fewer cores that you have (24 and 26, respectively) are much more affordable and/or common. >> > Therefore raise the default number of CPUs from 64 to 256 >> > by adding an arm64 specific option to override the generic default. >> >> Regardless of what the correct numbers for your chips are, I'd like >> to hear some other opinions on how high we should raise that default >> limit, both in arch/arm64/Kconfig and in the defconfig file. >> >> As I remember it, there is a noticeable cost for taking the limit beyond >> BITS_PER_LONG, both in terms of memory consumption and also >> runtime performance (copying and comparing CPU masks). > > OK, that explains the default. My unverified assumption is that > increasing the CPU masks wont be a noticable performance hit. The cpumask macros are rather subtle and are written to be as efficient as possible on configurations with 1, BITS_PER_LONG as well as large numbers of CPUs. There is also the CONFIG_CPUMASK_OFFSTACK option that trades (stack) memory consumption for CPU cycles and is usually used on configurations with more than 512 CPUs. > Also, I don't think that anyone who wants performance will use > defconfig. All server distributions would bump up the NR_CPUS anyway > and really small systems will probably need to tune the config > anyway. > > For me defconfig should produce a usable system, not with every last > driver configured but with all the basics like CPUs, networking, etc. > fully present. Agreed. If we can sacrifice a little bit of kernel performance in exchange for running on a wider range of machines, we should do that, but if either the CPU or memory cost is excessive for small machines, then I think it's better to sacrifice access to some of the CPUs on the larger systems. I would expect that the performance impact for running without SMP on ThunderX2 (52 CPUs instead of 224) is significant but also something we can live with as a non-optimized configuration. On my 32-thread x86 build box, disabling SMT costs under 20%, for larger configurations I would expect a smaller impact for similar workloads (because of Amdahl's law), but your SMT implementation may be better than AMD's. Arnd