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[209.132.180.67]) by mx.google.com with ESMTP id 4si11044179pgh.771.2018.03.07.00.37.04; Wed, 07 Mar 2018 00:37:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vnvjyu01; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751241AbeCGIfr (ORCPT + 99 others); Wed, 7 Mar 2018 03:35:47 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:53846 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751035AbeCGIfn (ORCPT ); Wed, 7 Mar 2018 03:35:43 -0500 Received: by mail-wm0-f65.google.com with SMTP id e194so3087360wmd.3 for ; Wed, 07 Mar 2018 00:35:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=FkmjR6pDnW7riZ+OtSsSDuREXbaxHh6g6uYfh/KD5ic=; b=Vnvjyu01JRhhQnd+YwIOxdk8xJrRa+tvGT4TMxnOpiL+9SReKcd8BWrK8yr+aPKZmR d3hLFEB0AGHS709LZFQYSDr9pHHDU2rTFGDcNm+DV0+Ey9E164hKXHI64huOzo2da8mv XEf1LCoBytJ7AyG/8WxuftvYE/3cetbwdyPb8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=FkmjR6pDnW7riZ+OtSsSDuREXbaxHh6g6uYfh/KD5ic=; b=YJjhN1SmgE51sexs8oJevGok3H+0/8SKvdT/eNaSqU++zXGBaObMfTNBBlYxBJTmy5 r0t2qLGLHvr5eQDHwSyAHCH/N2PhEfVEgSUTxCP1oEx9umPPBOs8/wmbHwAiWh3bvmhB /0x4FhPu4j8Mh8ttJMim9LzkV6w6vodSBHZZWCRBYL3HX8yDl8TS20iayyJdixBun1pz 3jdt9GQ6C371VcHa/x8lA/QJPUtKI4y0l6UZetgeM0/C8AJ++s9RxdhULWgkcpQ/dWWZ HOecCK7+86CnhYa/PZDoRW4r2N9cm0u0W25DjpuESx29cobD1IqBodRjEZ293P27y2Mx NZvg== X-Gm-Message-State: AElRT7EAHUlOr3M/XxCQ6Y5wlp7y+44X+9G2Yha/S5GbRzdwT2rIiDO9 lesBq+Ci2qGoy7aWy8BZTYU3r4aaRGM= X-Received: by 10.28.215.67 with SMTP id o64mr13279527wmg.159.1520411741800; Wed, 07 Mar 2018 00:35:41 -0800 (PST) Received: from dell ([2.27.35.218]) by smtp.gmail.com with ESMTPSA id b99sm26427044wrd.75.2018.03.07.00.35.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 Mar 2018 00:35:41 -0800 (PST) Date: Wed, 7 Mar 2018 08:35:39 +0000 From: Lee Jones To: Alexandre Torgue Cc: patrice.chotard@st.com, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, mcoquelin.stm32@gmail.com Subject: Re: [PATCH v2 0/6] Add mmc support for STM32F7 boards Message-ID: <20180307083538.vicxhbu72jex7zi6@dell> References: <1519901623-23216-1-git-send-email-patrice.chotard@st.com> <44ed2e2c-83f1-77f5-fa70-29c5525b9ee7@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <44ed2e2c-83f1-77f5-fa70-29c5525b9ee7@st.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 05 Mar 2018, Alexandre Torgue wrote: > Hi Patrice, > > On 03/01/2018 11:53 AM, patrice.chotard@st.com wrote: > > From: Patrice Chotard > > > > This series adds : > > _ SDIO pins definition for STM32F7 SoCs family > > _ add sdio1 DT entry for STM32F746 Discovery board > > _ add sdio1 DT entry for STM32F746 Evaluation board > > _ add sdio1 DT entry for STM32F769 Discovery board > > _ add SDMMC2 entry in stm32f7-rcc.h > > _ replace sdio2 hard coded value in stm32f746.dtsi > > > > v2: _ rename sdio_pins / sdio_od_pins to sdio_pins_a / sdio_od_pins_a > > and update board dts files accordingly. > > > > > > Patrice Chotard (6): > > ARM: dts: stm32: Add sdio pins definition for stm32f7 > > ARM: dts: stm32: Enable sdio1 for stm32f746-disco > > ARM: dts: stm32: Enable sdio1 for stm32f746-eval > > ARM: dts: stm32: Enable sdio1 for stm32f769-disco > > dt-bindings: mfd: Add STM32F7 SDMMC2 rcc entry > > ARM: dts: stm32: Fix sdio2 rcc hard coded value > > > > arch/arm/boot/dts/stm32746g-eval.dts | 17 ++++++++++ > > arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 62 ++++++++++++++++++++++++++++++++++ > > arch/arm/boot/dts/stm32f746-disco.dts | 19 +++++++++++ > > arch/arm/boot/dts/stm32f746.dtsi | 2 +- > > arch/arm/boot/dts/stm32f769-disco.dts | 19 +++++++++++ > > include/dt-bindings/mfd/stm32f7-rcc.h | 1 + > > 6 files changed, 119 insertions(+), 1 deletion(-) > > > Series applied on stm32-next. Even the MFD patch? -- Lee Jones Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog