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Violators will be prosecuted; Wed, 7 Mar 2018 09:36:12 -0700 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w27GaCSD13435278; Wed, 7 Mar 2018 09:36:12 -0700 Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 551A2BE03A; Wed, 7 Mar 2018 09:36:12 -0700 (MST) Received: from talon7.ibm.com (unknown [9.41.241.240]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP id F220CBE03B; Wed, 7 Mar 2018 09:36:11 -0700 (MST) From: Eddie James To: linux-kernel@vger.kernel.org Cc: linux-clk@vger.kernel.org, joel@jms.id.au, mturquette@baylibre.com, sboyd@kernel.org, Eddie James Subject: [PATCH] clk: aspeed: Prevent reset if clock is enabled Date: Wed, 7 Mar 2018 10:36:10 -0600 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 x-cbid: 18030716-0028-0000-0000-000009450F2B X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008629; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000254; SDB=6.00999643; UDB=6.00508487; IPR=6.00779049; MB=3.00019895; MTD=3.00000008; XFM=3.00000015; UTC=2018-03-07 16:36:14 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18030716-0029-0000-0000-000039E006AD Message-Id: <1520440570-25280-1-git-send-email-eajames@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-03-07_07:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1803070190 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to the Aspeed specification, the reset and enable sequence should be done when the clock is stopped. The specification doesn't define behavior if the reset is done while the clock is enabled. From testing on the AST2500, the LPC Controller has problems if the clock is reset while enabled. Therefore, check whether the clock is enabled or not before performing the reset and enable sequence in the Aspeed clock driver. Signed-off-by: Eddie James --- drivers/clk/clk-aspeed.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 9f7f931..a13054d 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -212,6 +212,12 @@ static int aspeed_clk_enable(struct clk_hw *hw) u32 clk = BIT(gate->clock_idx); u32 rst = BIT(gate->reset_idx); u32 enval; + u32 reg; + + /* Only reset/enable/unreset if clock is stopped */ + regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); + if (!(reg & clk)) + return 0; spin_lock_irqsave(gate->lock, flags); -- 1.8.3.1