Received: by 10.223.185.116 with SMTP id b49csp5502619wrg; Wed, 7 Mar 2018 12:56:44 -0800 (PST) X-Google-Smtp-Source: AG47ELsotj+Mg9j0wImfaefUptO1mSLUJGwntqo3oc0CRJKhagWxAvh82bymo9oKXOfuBtMGlcTP X-Received: by 2002:a17:902:69cf:: with SMTP id m15-v6mr22095888pln.104.1520456204817; Wed, 07 Mar 2018 12:56:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520456204; cv=none; d=google.com; s=arc-20160816; b=G4Ksqct/VLMcQTZpoE8nTGqrj33UJGv8OCuhghJC73SF7cqc79AuHzhpIAVK1ficgb jKbqD8NOMIAwsLI5CjGPXn3th0GZMwn02vbcjIQmwRvJf87aCrA5cxPu9ZK2EXwkMWVs F9dWNNk1zlIpVYfGdKCnIeedwEGMGqAlaIt6c684FMoErKyi/bgVGvJW5wrcJNyz2msj M/upWLyxal+ju1OSIZa7LJuh8kuKZbDf7WWBm+TfOm6z1bxFQKMixOqKCyMzfkj6YfVL HX9rKBLmDIh6M8vf9nAy5nitSHZICTan4I8+bO7jhKt1NialOV5IzPBsV2TWEdDkWKL7 ZDeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:dmarc-filter:dkim-signature:dkim-signature :arc-authentication-results; bh=n2Iwza1wDirRVUuZ+SF3iqSZEStScyWZIiv2U4xKbm4=; b=M8If/hWaPc8bat7kyHy9ii5x2cDHp8m2oK8nxI3UILFOxUfJUHrXf6sPUSj6LF2cua XJLL4Liq4jPb10nJjKzgLfsqzuQO4vTyCwk+bRBRarEgodftBwxp4bRw4h9BT7vDeMSx OY57mwjfJEx+bTLlHnvuDHcBso4OW7bQez+zXLoyEpJckuy/T2MyZX5fx+yyBd7t4fJA G2HZJ78K/Lw0qFgcW2oEjiAoMzdfLORdt7TUz00RsObuD+jruTKwqkLUPM9jrFAOvUv1 6xF48bV6oiet6F9ThR+IifnHVqCS/0zefObGgXRj+sVPbdJgXkRu/iDNHsnHk5gzCyXw oaqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=bDjqhCLE; dkim=pass header.i=@codeaurora.org header.s=default header.b=QIbBU1YI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a33-v6si13426709pld.653.2018.03.07.12.56.30; Wed, 07 Mar 2018 12:56:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=bDjqhCLE; dkim=pass header.i=@codeaurora.org header.s=default header.b=QIbBU1YI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934639AbeCGUyY (ORCPT + 99 others); Wed, 7 Mar 2018 15:54:24 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:51836 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934240AbeCGUyS (ORCPT ); Wed, 7 Mar 2018 15:54:18 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 313B56022C; Wed, 7 Mar 2018 20:54:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520456058; bh=qmTtlJOQOK+DnFKBo3auhkbtxg/yTB1heUfN5kDws7I=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bDjqhCLE09NPNRQLL3/VgTNYhpkUtA70qep4ZjecKMdhySKKbuNLktU6xxiu/ySKP KzSs1w3kHOjlvdYEiFDRKybjrHiUim2pGakrAX3A6LxCYHfWdT4Mg9preVycTk7nEP gcyaNAJW8/0Ki7G0vB+alcmg43gihn1BfqUyHJAw= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F30B06022C; Wed, 7 Mar 2018 20:54:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520456057; bh=qmTtlJOQOK+DnFKBo3auhkbtxg/yTB1heUfN5kDws7I=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=QIbBU1YI9qN8lIbepyPQUrFmL2lZU6F5fAXj6oDJLrcldGd4JMyERJGS3EZby5t+O 1eO6EJOmQ1FwNhnr94f+CqNtpCjCv63NQfukOkcGOLdGGrU6Ai3x06TLaB1Js4c+1J tnYwSpg8nzvZAL6TkxXuMEhU901Co9fuNMawhMKY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F30B06022C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org Date: Wed, 7 Mar 2018 13:54:16 -0700 From: Lina Iyer To: Stephen Boyd Cc: andy.gross@linaro.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, rnayak@codeaurora.org, bjorn.andersson@linaro.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 02/10] dt-bindings: introduce RPMH RSC bindings for Qualcomm SoCs Message-ID: <20180307205416.GH4930@codeaurora.org> References: <20180302164317.10554-1-ilina@codeaurora.org> <20180302164317.10554-3-ilina@codeaurora.org> <152037541468.218381.12480897609076588560@swboyd.mtv.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <152037541468.218381.12480897609076588560@swboyd.mtv.corp.google.com> User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 06 2018 at 15:30 -0700, Stephen Boyd wrote: >Quoting Lina Iyer (2018-03-02 08:43:09) >> Add device binding documentation for Qualcomm Technology Inc's RPMH RSC >> driver. The hardware block is used for communicating resource state > >s/driver/hardware/ > Ok. >> requests for shared resources. >> >> Cc: devicetree@vger.kernel.org >> Signed-off-by: Lina Iyer >> --- >> >> Changes in v2: >> - Amend text to describe the registers in reg property >> - Add reg-names for the registers >> - Update examples to use GIC_SPI in interrupts instead of 0 >> - Rephrase incorrect description >> >> Changes in v3: >> - Fix unwanted capitalization >> - Remove clients from the examples, this doc does not describe >> them >> - Rephrase introductory paragraph >> - Remove hardware specifics from DT bindings >> --- >> .../devicetree/bindings/arm/msm/rpmh-rsc.txt | 131 +++++++++++++++++++++ >> 1 file changed, 131 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/msm/rpmh-rsc.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/msm/rpmh-rsc.txt b/Documentation/devicetree/bindings/arm/msm/rpmh-rsc.txt >> new file mode 100644 >> index 000000000000..afd3817cc615 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/msm/rpmh-rsc.txt > >Shouldn't this go into bindings/soc/qcom/ ? > Didn;t realize the location. Thanks for pointing out. > + >> +Requests can be made for the state of a resource, when the subsystem is active >> +or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state >> +will be an aggregate of the sleep votes from each of those subsystem. Drivers > >s/subsystem/subsystems/ >s/Drivers/Clients/ ? > Ok >> +may request a sleep value for their shared resources in addition to the active >> +mode requests. >> + >> +Control requests are instance specific requests that may or may not reach an >> +accelerator. Only one platform device in Linux can request a control channel >> +on a DRV. > >Not sure what this last sentence has to do with the DT binding. We >generally try to avoid saying 'Linux' or 'driver' in DT binding >documents, because they usually document hardware. > This para can go away. >> + >> +Properties: >> + >> +- compatible: >> + Usage: required >> + Value type: >> + Definition: Should be "qcom,rpmh-rsc". >> + >> +- reg: >> + Usage: required >> + Value type: >> + Definition: The first register specifies the base address of the DRV. >> + The second register specifies the start address of the >> + TCS. >> + >> +- reg-names: >> + Usage: required > >optional? > No, it is required. Driver has been using the by_name for clarity. >> + Value type: >> + Definition: Maps the register specified in the reg property. Must be >> + "drv" and "tcs". >> + >> +- interrupts: >> + Usage: required >> + Value type: >> + Definition: The interrupt that trips when a message complete/response >> + is received for this DRV from the accelerators. >> + >> +- qcom,drv-id: >> + Usage: required >> + Value type: >> + Definition: the id of the DRV in the RSC block. >> + >> +- qcom,tcs-config: >> + Usage: required >> + Value type: >> + Definition: the tuple defining the configuration of TCS. >> + Must have 2 cells which describe each TCS type. >> + . >> + The order of the TCS must match the hardware >> + configuration. >> + - Cell #1 (TCS Type): TCS types to be specified - >> + SLEEP_TCS >> + WAKE_TCS >> + ACTIVE_TCS >> + CONTROL_TCS >> + - Cell #2 (Number of TCS): >> + >> +- label: >> + Usage: optional >> + Value type: >> + Definition: Name for the RSC. The name would be used in trace logs. >> + >> +Drivers that want to use the RSC to communicate with RPMH must specify their >> +bindings as child of the RSC controllers they wish to communicate with. > >Is that going to work for drivers that want to talk to two or more RSCs? >I suppose that they'll have to hook up into some sort of framework like >clk or regulator and then drivers that want to use two RSCs for those >things would be linked to those sub-device drivers with the normal clk >or regulator bindings? > Correct. This follows the same model as RPM SMD driver. >> + >> +Example 1: >> + >> +For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the >> +register offsets for DRV2 start at 0D00, the register calculations are like >> +this - >> +First tuple: 0x179C0000 + 0x10000 * 2 = 0x179E0000 >> +Second tuple: 0x179E0000 + 0xD00 = 0x179E0D00 >> + >> + apps_rsc: rsc@179e000 { >> + label = "apps_rsc"; >> + compatible = "qcom,rpmh-rsc"; >> + reg = <0x179e0000 0x10000>, <0x179e0d00 0x3000>; >> + reg-names = "drv", "tcs"; >> + interrupts = ; >> + qcom,drv-id = <2>; >> + qcom,tcs-config = , >> + , >> + , >> + ; > >Could qcom,tcs-config become something more like below? > > #qcom,sleep-tcs = <3>; > #qcom,wake-tcs = <3>; > #qcom,active-tcs = <2>; > #qcom,control-tcs = <1>; > >I don't really understand the binding design to have many cells with the >*_TCS defines indicating what comes next. > This format helps preserve the order in which the TCS are designed in the firmware. Thats additional information that is described by the cells. Thanks, Lina