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[209.132.180.67]) by mx.google.com with ESMTP id r9si14647194pfg.165.2018.03.07.16.00.04; Wed, 07 Mar 2018 16:00:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=mihYzx5W; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755121AbeCGX5l (ORCPT + 99 others); Wed, 7 Mar 2018 18:57:41 -0500 Received: from mail-pl0-f46.google.com ([209.85.160.46]:40029 "EHLO mail-pl0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755099AbeCGX5j (ORCPT ); Wed, 7 Mar 2018 18:57:39 -0500 Received: by mail-pl0-f46.google.com with SMTP id i6-v6so2301413plt.7 for ; Wed, 07 Mar 2018 15:57:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:from:to; bh=TDDWzDDfQDvYpM6YR+0V7vNXIi/Yv+twxG3SYlALTmk=; b=mihYzx5W8pSYC3jjl/Pxc3SzF9IqrwRNh1b8vXar+ZCoGqYtdkRNvfESxIdVUunUm/ 8Z12pnc3i2DSwGUU58iv2ZQVIVkQLk89V206++nt85Rs1EUUV9UwMVA/k3Ics8iTBgvG XlLXthNEXY8bKTqXbCnfN7z0UJbqO8ydYrSxKX/0JhpNM1Y/vIo/yrjkfDAp6F2OpltM dY/Gm6kd+PuGH4TK/uGd2QVzPIBsjtyGrKwwo6d83h+7BVLMepadHJw1cZyBockOhj6p hwUMQO5HPODhGwWdBIEsxz+BqWJ0CS0gbY7WBdDH7J5Z8aQ1k7N1kYnrTWAVEvKc7YbM XPzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:from:to; bh=TDDWzDDfQDvYpM6YR+0V7vNXIi/Yv+twxG3SYlALTmk=; b=T/GzDaV43EYORAF+6UOF90iaZKj9GjCgpyiIHYCoW2NVdhHvFv1YuWy83uHE5LSJpH F9XTeprcoEovM8TUc4SPMtwr7C0JO7xKGk6S/sMMtezO4qB3LTeZL0spgkn7OtNVTqN2 ISVFEAFF2uf4K2iQMGyki1qgTNk7L7inR8iJAs3RQNQ+S1nC4bFG1ndK2YWb3uLNy51v 67RHABXnoFWRWGFK2wz9vrWw2cXXIi+4ejlQQzrbPDHDjIqKwyfpj0hXKiLPA2WWYyUM +eFcv6CpCcEKg6fbNW9kwjQZM7nMCsyqtlcrNoZv0ThWqBzTK5krxgFSY6I6CGKX7Nzf h4tg== X-Gm-Message-State: APf1xPCbgp7F4r5tZlQ3jVX2fD+1+S4H61OjE765HNqBt9CSN4hIqNBg o21xEOTUk2m8Fll348AyVSBgZQ== X-Received: by 2002:a17:902:501:: with SMTP id 1-v6mr21983525plf.283.1520467058643; Wed, 07 Mar 2018 15:57:38 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 76sm41268230pfm.124.2018.03.07.15.57.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Mar 2018 15:57:37 -0800 (PST) Subject: Make set_handle_irq and handle_arch_irq generic, v3 Date: Wed, 7 Mar 2018 15:57:26 -0800 Message-Id: <20180307235731.22627-1-palmer@sifive.com> X-Mailer: git-send-email 2.16.1 From: Palmer Dabbelt To: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openrisc@lists.librecores.org, linux-riscv@lists.infradead.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is my third version of this patch set, but the original cover letter is still the most relevant description I can come up with. This patch set has been sitting around for a while, but it got a bit lost in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry point for interrupt handling) to our first-level interrupt controller. While this isn't completely crazy (as the first-level interrupt controller is specified by the ISA), it is a bit awkward. This patch set decouples our trap handler from our first-level IRQ chip driver by copying what a handful of other architectures are doing. This does add an additional load to the interrupt handling path, but there's a handful of performance problems in there that I've been meaning to look at so I don't mind adding another one for now. The advantage is that our irqchip driver is decoupled from our arch port, at least at compile time. I've build tested this with defconfigs on all the modified architectures after both patch 1 and 5. I've left the old acks in for the later patches as the patch set has changed very little since I last submitted it. Changes since v2: * This is now called CONFIG_GENERIC_IRQ_MULTI_HANDLER instead of MULTI_IRQ_HANDLER. * Rather than converting the ARM code to generic code, this adds new generic code (based on the ARM implementation) and then provides separate patches to convert each architecture over to use CONFIG_GENERIC_IRQ_MULTI_HANDLER. Changes since v1: * I based this on arm instead of arm64, which means we guard the selection of these routines with CONFIG_MULTI_IRQ_HANDLER. * The changes are in kernel/irq/handle.c and include/linux/irq.h instead of lib. * I've converted the arm, arm64, and openrisc ports to use the generic versions of these routines. [PATCH v3 1/5] irq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER [PATCH v3 2/5] RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER [PATCH v3 3/5] arm: Convert to GENERIC_IRQ_MULTI_HANDLER [PATCH v3 4/5] arm64: Use the new GENERIC_IRQ_MULTI_HANDLER [PATCH v3 5/5] openrisc: Use the new GENERIC_IRQ_MULTI_HANDLER