Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
In-Reply-To: <CACPK8Xe5rVtB6hUo4xW9qSz-T+kehvXSRv5g1_6KOO=BYr8Qwg@mail.gmail.com>
References: <1520440570-25280-1-git-send-email-eajames@linux.vnet.ibm.com> <CACPK8Xe5rVtB6hUo4xW9qSz-T+kehvXSRv5g1_6KOO=BYr8Qwg@mail.gmail.com>
From:   Joel Stanley <joel@jms.id.au>
Date:   Thu, 8 Mar 2018 14:23:44 +1030
Message-ID: <CACPK8XdK5EWvuN7Cu+q8-BrWAbeGTz_kV0UW1sWj=jv5whD5Hw@mail.gmail.com>
Subject: Re: [PATCH] clk: aspeed: Prevent reset if clock is enabled
To:     Eddie James <eajames@linux.vnet.ibm.com>
Cc:     Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-clk@vger.kernel.org,
        Michael Turquette <mturquette@baylibre.com>, sboyd@kernel.org,
        Lei YU <mine260309@gmail.com>,
        Ryan Chen <ryan_chen@aspeedtech.com>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Thu, Mar 8, 2018 at 2:12 PM, Joel Stanley <joel@jms.id.au> wrote:
> Hi Eddie,
>
> On Thu, Mar 8, 2018 at 3:06 AM, Eddie James <eajames@linux.vnet.ibm.com> wrote:
>> According to the Aspeed specification, the reset and enable sequence
>> should be done when the clock is stopped. The specification doesn't
>> define behavior if the reset is done while the clock is enabled.
>>
>> From testing on the AST2500, the LPC Controller has problems if the
>> clock is reset while enabled.
>>
>> Therefore, check whether the clock is enabled or not before performing
>> the reset and enable sequence in the Aspeed clock driver.
>>
>> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
>> ---
>>  drivers/clk/clk-aspeed.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
>> index 9f7f931..a13054d 100644
>> --- a/drivers/clk/clk-aspeed.c
>> +++ b/drivers/clk/clk-aspeed.c
>> @@ -212,6 +212,12 @@ static int aspeed_clk_enable(struct clk_hw *hw)
>>         u32 clk = BIT(gate->clock_idx);
>>         u32 rst = BIT(gate->reset_idx);
>>         u32 enval;
>> +       u32 reg;
>> +
>> +       /* Only reset/enable/unreset if clock is stopped */
>> +       regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);
>> +       if (!(reg & clk))
>> +               return 0;
>
> This doesn't generalise to all of the clocks, as some clocks use set
> to disable. Perhaps we could do something like this:
>
>        /* Only reset/enable/unreset if clock is stopped. The LPC clock
> on ast2500 has issues otherwise */

We've seen this on both the ast2400 and ast2500, so if you do take my
suggestion perhaps just say "The LPC clock has issues otherwise".

>        enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
>        regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);
>        if ((reg & clk) == enval) {
>                spin_unlock_irqrestore(gate->lock, flags);
>                return 0;
>        }
>
> I think we should also do this operation under the lock.
>
> Please cc Ryan Chen <ryan_chen@aspeedtech.com> so he can confirm that
> this workaround is valid, and credit Lei who spent a lot of time
> investigating this issue. Perhaps "Root-caused-by".
>
> Cheers,
>
> Joel