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From:   Ganapatrao Kulkarni <gklkml16@gmail.com>
Date:   Thu, 8 Mar 2018 09:44:59 +0530
Message-ID: <CAKTKpr7HgsdZ90k0_evSq_aZW-uGSKwLndHOQ2Jahajj3Gkc0Q@mail.gmail.com>
Subject: Re: [PATCH] perf vendor events arm64: Enable JSON events for
 ThunderX2 B0
To:     William Cohen <wcohen@redhat.com>
Cc:     Arnaldo Carvalho de Melo <acme@kernel.org>, mark.rutland@arm.com,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        John Garry <john.garry@huawei.com>,
        Will Deacon <Will.Deacon@arm.com>,
        linux-kernel@vger.kernel.org,
        Peter Zijlstra <peterz@infradead.org>,
        Robert Richter <Robert.Richter@cavium.com>,
        Ingo Molnar <mingo@redhat.com>, jnair@caviumnetworks.com,
        Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>,
        Jiri Olsa <jolsa@redhat.com>,
        linux-arm-kernel@lists.infradead.org
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On Thu, Mar 8, 2018 at 12:01 AM, William Cohen <wcohen@redhat.com> wrote:
> On 03/07/2018 12:35 PM, Ganapatrao Kulkarni wrote:
>> Hi Will Cohen,
>>
>> On Wed, Mar 7, 2018 at 8:08 PM, Arnaldo Carvalho de Melo
>> <acme@kernel.org> wrote:
>>> Em Wed, Mar 07, 2018 at 09:32:05AM -0500, William Cohen escreveu:
>>>> On 03/07/2018 06:08 AM, Ganapatrao Kulkarni wrote:
>>>>> There is MIDR change on ThunderX2 B0, adding an entry to mapfile
>>>>> to enable JSON events for B0.
>>>>>
>>>>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>>>
>>> Ganapatrao, can you please take this in consideration and if agreeing
>>> send a v2 patch?
>>>
>>> With that I can add an Acked-by: wcohen, Right?
>>>
>>> - Arnaldo
>>>>> ---
>>>>>  tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>>>>>  1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/per=
f/pmu-events/arch/arm64/mapfile.csv
>>>>> index e61c9ca..93c5d14 100644
>>>>> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>>> @@ -13,4 +13,5 @@
>>>>>  #
>>>>>  #Family-model,Version,Filename,EventType
>>>>>  0x00000000420f5160,v1,cavium,core
>>>>> +0x00000000430f0af0,v1,cavium,core
>>>>>  0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
>>>>>
>>>>
>>>> Hi,
>>>> Like the cortex-a53 the last digit '0' of the match for the MIDR shoul=
d be replaced with [[:xdigit:]] to allow for possible future revisions of c=
hip:
>>
>> for arm64 implementation,  bits 3:0(Revision) and bits 23:20(Variant)
>> are ignored/dont-care.
>
> Thanks for pointing that out.  See the code masking out those bits in lin=
ux/toos/perf/arch/util/header.c. For the ppc64 it just copies the equivalen=
t of the MIDR including the revision bits. Thus, the need for regular expre=
ssion matching to avoid having to create a new entry for each revision.

It is same for arm64 too, there is no need to add an entry for every
revision change,  need to add when part number changes.
This patch is not intended to add entry for revision change, the fact
of the matter is that, there  is complete MIDR change (vulcan to
thunderx2) in B0.
as per current arm64
implementation(.tools/perf/arch/arm64/util/header.c), it is not
required to have any dontcare marking in mapfile for revision/variant
bits.

thanks
Ganapat

>
> -Will
>
>>
>>>>
>>>> 0x00000000430f0af[[:xdigit:]],v1,cavium,core
>>>>
>>>>
>>>> -Will Cohen
>>>
>>
>> thanks
>> Ganapat
>>> _______________________________________________
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>>> linux-arm-kernel@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>