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From:   Sasha Levin <Alexander.Levin@microsoft.com>
To:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "stable@vger.kernel.org" <stable@vger.kernel.org>
CC:     Jerome Brunet <jbrunet@baylibre.com>,
        "David S . Miller" <davem@davemloft.net>,
        Sasha Levin <Alexander.Levin@microsoft.com>
Subject: [PATCH AUTOSEL for 4.14 31/67] net: phy: meson-gxl: check phy_write
 return value
Thread-Topic: [PATCH AUTOSEL for 4.14 31/67] net: phy: meson-gxl: check
 phy_write return value
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Date:   Thu, 8 Mar 2018 04:57:45 +0000
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From: Jerome Brunet <jbrunet@baylibre.com>

[ Upstream commit 9042b46eda33ef5db3cdfc9e12b3c8cabb196141 ]

Always check phy_write return values. Better to be safe than sorry

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
---
 drivers/net/phy/meson-gxl.c | 50 ++++++++++++++++++++++++++++++++++-------=
----
 1 file changed, 38 insertions(+), 12 deletions(-)

diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index 1ea69b7585d9..7ddb709f69fc 100644
--- a/drivers/net/phy/meson-gxl.c
+++ b/drivers/net/phy/meson-gxl.c
@@ -25,27 +25,53 @@
=20
 static int meson_gxl_config_init(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Enable Analog and DSP register Bank access by */
-	phy_write(phydev, 0x14, 0x0000);
-	phy_write(phydev, 0x14, 0x0400);
-	phy_write(phydev, 0x14, 0x0000);
-	phy_write(phydev, 0x14, 0x0400);
+	ret =3D phy_write(phydev, 0x14, 0x0000);
+	if (ret)
+		return ret;
+	ret =3D phy_write(phydev, 0x14, 0x0400);
+	if (ret)
+		return ret;
+	ret =3D phy_write(phydev, 0x14, 0x0000);
+	if (ret)
+		return ret;
+	ret =3D phy_write(phydev, 0x14, 0x0400);
+	if (ret)
+		return ret;
=20
 	/* Write Analog register 23 */
-	phy_write(phydev, 0x17, 0x8E0D);
-	phy_write(phydev, 0x14, 0x4417);
+	ret =3D phy_write(phydev, 0x17, 0x8E0D);
+	if (ret)
+		return ret;
+	ret =3D phy_write(phydev, 0x14, 0x4417);
+	if (ret)
+		return ret;
=20
 	/* Enable fractional PLL */
-	phy_write(phydev, 0x17, 0x0005);
-	phy_write(phydev, 0x14, 0x5C1B);
+	ret =3D phy_write(phydev, 0x17, 0x0005);
+	if (ret)
+		return ret;
+	ret =3D phy_write(phydev, 0x14, 0x5C1B);
+	if (ret)
+		return ret;
=20
 	/* Program fraction FR_PLL_DIV1 */
-	phy_write(phydev, 0x17, 0x029A);
-	phy_write(phydev, 0x14, 0x5C1D);
+	ret =3D phy_write(phydev, 0x17, 0x029A);
+	if (ret)
+		return ret;
+	ret =3D phy_write(phydev, 0x14, 0x5C1D);
+	if (ret)
+		return ret;
=20
 	/* Program fraction FR_PLL_DIV1 */
-	phy_write(phydev, 0x17, 0xAAAA);
-	phy_write(phydev, 0x14, 0x5C1C);
+	ret =3D phy_write(phydev, 0x17, 0xAAAA);
+	if (ret)
+		return ret;
+	ret =3D phy_write(phydev, 0x14, 0x5C1C);
+	if (ret)
+		return ret;
=20
 	return 0;
 }
--=20
2.14.1