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[209.132.180.67]) by mx.google.com with ESMTP id b10si13293098pgn.140.2018.03.08.08.52.43; Thu, 08 Mar 2018 08:52:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=lR8FH0if; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934357AbeCHQtX (ORCPT + 99 others); Thu, 8 Mar 2018 11:49:23 -0500 Received: from mail-pl0-f51.google.com ([209.85.160.51]:37243 "EHLO mail-pl0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933906AbeCHQtV (ORCPT ); Thu, 8 Mar 2018 11:49:21 -0500 Received: by mail-pl0-f51.google.com with SMTP id w12-v6so3628311plp.4 for ; Thu, 08 Mar 2018 08:49:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=vVrQ9zcOtn4OA26sWsDpm61m3TIPsv/RlGCsr/91ZNo=; b=lR8FH0ifkhuL7R0D+N0c3g+jy0axD4iTgdJJ0wLY14unreHGkcujaxivYKO8WV3quX 7XjtR/5NKiBQnb2JlT3vN+8INoji6p3z+QUKagmgRsPLZbVSKSfQsyaPt/Rn8EDZEG6r Sx5HuyWeyMVobc9ne9T/JdQRc+FDAQiX0RtoA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=vVrQ9zcOtn4OA26sWsDpm61m3TIPsv/RlGCsr/91ZNo=; b=WgJ2+5AV1TSXFBzNkw20QUjbiN059tSMRhq2JxcrvCcvOyeJ3lxi/gOiB+CtMhJ2iI jdjjqROiQZsthDh4FUdOThtQL7gYpBwgP48+C0qKxu2aPloPTI+bwxfhcfwHnLrwFfN0 bVpp1C7g6gxWH6xtHV7HYXikE5Xsyh2445fk2gEEKGtcxP1tagwFfdLbReJ2fEibc7Dq AiR/6LCDWgwAcT8fLcdHmrXNhnc9ytiq1vvG/ifgU7gEWtP7l1OLJOux9QX11HQ1nrah CB5yaIdhoK5hbDM9ZWd6CekIYrKMYiJdHqGPb6ylOhQyHeOAxRPbB4V7TUbIXuK+kUL6 Jpiw== X-Gm-Message-State: APf1xPDR3LWllgM07B7IA+mvf+0R2tx8HuuGMD5D1O9ir8Ub94tSTCfK eAns7uGZcUjfsbfgoooihgBJ+v8C+Tk= X-Received: by 2002:a17:902:3303:: with SMTP id a3-v6mr24418927plc.399.1520527760949; Thu, 08 Mar 2018 08:49:20 -0800 (PST) Received: from rodete-desktop-imager.corp.google.com ([2620:0:1000:1501:bc2f:3082:9938:5d41]) by smtp.gmail.com with ESMTPSA id w63sm35559975pgb.80.2018.03.08.08.49.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Mar 2018 08:49:20 -0800 (PST) Date: Thu, 8 Mar 2018 08:49:18 -0800 From: Brian Norris To: Felipe Balbi Cc: William Wu , gregkh@linuxfoundation.org, Roger Quadros , heiko@sntech.de, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, frank.wang@rock-chips.com, huangtao@rock-chips.com, dianders@google.com, briannorris@google.com, groeck@google.com, daniel.meng@rock-chips.com, John.Youn@synopsys.com, lin.huang@rock-chips.com Subject: Re: [PATCH] usb: dwc3: core: power on PHYs before initializing core Message-ID: <20180308164916.GA65031@rodete-desktop-imager.corp.google.com> References: <1515729616-8639-1-git-send-email-william.wu@rock-chips.com> <87ina6vodf.fsf@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87ina6vodf.fsf@linux.intel.com> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Mar 08, 2018 at 12:43:40PM +0200, Felipe Balbi wrote: > William Wu writes: > > The dwc3_core_init() gets the PHYs and initializes the PHYs with > > the usb_phy_init() and phy_init() functions before initializing > > core, and power on the PHYs after core initialization is done. > > > > However, some platforms (e.g. Rockchip RK3399 DWC3 with Type-C > > USB3 PHY), it needs to do some special operation while power on > > the Type-C PHY before initializing DWC3 core. It's because that > > the RK3399 Type-C PHY requires to hold the DWC3 controller in > > reset state to keep the PIPE power state in P2 while configuring > > the Type-C PHY, otherwise, it may cause waiting for the PIPE ready > > timeout. In this case, if we power on the PHYs after the DWC3 core > > initialization is done, the core will be reset to uninitialized > > state after power on the PHYs. > > > > Fix this by powering on the PHYs before initializing core. And > > because the GUID register may also be reset in this case, so we > > need to configure the GUID register after powering on the PHYs. > > > > Signed-off-by: William Wu > > does this cause any regressions for your boards? I'm not Roger, but I believe it was determined we don't need this for the Rockchip systems for which William was originally sending this. At least not right now. I believe our PHY init problems were mostly resolved in other ways. (Although I hear USB is currently pretty broken around suspend/resume for us on -next. Likely unrelated.) I guess we never clearly replied stating the above. I hope this isn't merged anywhere? Or I guess it's no problem to me at the moment, but it might be needless churn. Brian