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[209.132.180.67]) by mx.google.com with ESMTP id 64-v6si15376943ply.209.2018.03.08.10.05.42; Thu, 08 Mar 2018 10:05:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936114AbeCHSEo (ORCPT + 99 others); Thu, 8 Mar 2018 13:04:44 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:41884 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752193AbeCHSEn (ORCPT ); Thu, 8 Mar 2018 13:04:43 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B481B1529; Thu, 8 Mar 2018 10:04:42 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 78DF93F24A; Thu, 8 Mar 2018 10:04:42 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 23A2B1AE53D6; Thu, 8 Mar 2018 18:04:47 +0000 (GMT) Date: Thu, 8 Mar 2018 18:04:47 +0000 From: Will Deacon To: Toshi Kani Cc: mhocko@suse.com, akpm@linux-foundation.org, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, bp@suse.de, catalin.marinas@arm.com, guohanjun@huawei.com, wxf.wang@hisilicon.com, linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] mm/vmalloc: Add interfaces to free unused page table Message-ID: <20180308180446.GF14918@arm.com> References: <20180307183227.17983-1-toshi.kani@hpe.com> <20180307183227.17983-2-toshi.kani@hpe.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180307183227.17983-2-toshi.kani@hpe.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Toshi, Thanks for the patches! On Wed, Mar 07, 2018 at 11:32:26AM -0700, Toshi Kani wrote: > On architectures with CONFIG_HAVE_ARCH_HUGE_VMAP set, ioremap() > may create pud/pmd mappings. Kernel panic was observed on arm64 > systems with Cortex-A75 in the following steps as described by > Hanjun Guo. > > 1. ioremap a 4K size, valid page table will build, > 2. iounmap it, pte0 will set to 0; > 3. ioremap the same address with 2M size, pgd/pmd is unchanged, > then set the a new value for pmd; > 4. pte0 is leaked; > 5. CPU may meet exception because the old pmd is still in TLB, > which will lead to kernel panic. > > This panic is not reproducible on x86. INVLPG, called from iounmap, > purges all levels of entries associated with purged address on x86. > x86 still has memory leak. > > Add two interfaces, pud_free_pmd_page() and pmd_free_pte_page(), > which clear a given pud/pmd entry and free up a page for the lower > level entries. > > This patch implements their stub functions on x86 and arm64, which > work as workaround. > > Reported-by: Lei Li > Signed-off-by: Toshi Kani > Cc: Catalin Marinas > Cc: Wang Xuefeng > Cc: Will Deacon > Cc: Hanjun Guo > Cc: Michal Hocko > Cc: Andrew Morton > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: "H. Peter Anvin" > Cc: Borislav Petkov > --- > arch/arm64/mm/mmu.c | 10 ++++++++++ > arch/x86/mm/pgtable.c | 20 ++++++++++++++++++++ > include/asm-generic/pgtable.h | 10 ++++++++++ > lib/ioremap.c | 6 ++++-- > 4 files changed, 44 insertions(+), 2 deletions(-) [...] > diff --git a/lib/ioremap.c b/lib/ioremap.c > index b808a390e4c3..54e5bbaa3200 100644 > --- a/lib/ioremap.c > +++ b/lib/ioremap.c > @@ -91,7 +91,8 @@ static inline int ioremap_pmd_range(pud_t *pud, unsigned long addr, > > if (ioremap_pmd_enabled() && > ((next - addr) == PMD_SIZE) && > - IS_ALIGNED(phys_addr + addr, PMD_SIZE)) { > + IS_ALIGNED(phys_addr + addr, PMD_SIZE) && > + pmd_free_pte_page(pmd)) { I find it a bit weird that we're postponing this to the subsequent map. If we want to address the break-before-make issue that was causing a panic on arm64, then I think it would be better to do this on the unmap path to avoid duplicating TLB invalidation. Will