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From:   Shea Levy <shea@shealevy.com>
To:     Palmer Dabbelt <palmer@sifive.com>
Cc:     linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH] riscv: Implement free_initrd_mem.
In-Reply-To: <mhng-dd74e051-4ddc-4ca9-bfd6-d0c1ea5eb4f4@palmer-si-x1c4>
References: <mhng-dd74e051-4ddc-4ca9-bfd6-d0c1ea5eb4f4@palmer-si-x1c4>
Date:   Thu, 08 Mar 2018 14:47:08 -0500
Message-ID: <874llquz7n.fsf@xps13.shealevy.com>
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Palmer Dabbelt <palmer@sifive.com> writes:

> On Thu, 08 Mar 2018 11:14:52 PST (-0800), shea@shealevy.com wrote:
>> Hi Palmer,
>>
>> Palmer Dabbelt <palmer@sifive.com> writes:
>>
>>> On Tue, 20 Feb 2018 05:50:43 PST (-0800), shea@shealevy.com wrote:
>>>> Signed-off-by: Shea Levy <shea@shealevy.com>
>>>> ---
>>>>  arch/riscv/mm/init.c | 6 ++++++
>>>>  1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
>>>> index c77df8142be2..1c832b541e95 100644
>>>> --- a/arch/riscv/mm/init.c
>>>> +++ b/arch/riscv/mm/init.c
>>>> @@ -66,5 +66,11 @@ void free_initmem(void)
>>>>  #ifdef CONFIG_BLK_DEV_INITRD
>>>>  void free_initrd_mem(unsigned long start, unsigned long end)
>>>>  {
>>>> +	if (start =3D=3D initrd_start)
>>>> +		start =3D round_down(start, PAGE_SIZE);
>>>> +	if (end =3D=3D initrd_end)
>>>> +		end =3D round_up(end, PAGE_SIZE);
>>>> +
>>>> +	free_reserved_area((void *)start, (void *)end, -1, "initrd");
>>>>  }
>>>>  #endif /* CONFIG_BLK_DEV_INITRD */
>>>
>>> It looks like everyone is doing something slightly different here:
>>>
>>> * arm64 doesn't round to a page size, and has keep_initrd.
>>> * arm calls poison_init_mem(), and has keep_initrd.
>>> * sparc64 doesn't round, and doesn't have a keep_initrd.
>>> * mips doesn't round, and doesn't have a keep_initrd.
>>> * x86 rounds end to a page size but not start, and doesn't have a keep_=
initrd.
>>>
>>> It feels like this should be something generic.  I'm adding linux-kerne=
l to see=20
>>> what people think.
>>
>> Should I try to whip up something generic?
>
> I think that'd be best.  Nobody has said anything specific, but it's gene=
rally=20
> been suggested to take bits that we copy into our port and make them gene=
ric.=20=20
> If there's no clean way do to so then I'm OK taking this, though.

OK, will add it to my queue.

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