Received: by 10.223.185.116 with SMTP id b49csp134732wrg;
        Thu, 8 Mar 2018 14:17:13 -0800 (PST)
X-Google-Smtp-Source: AG47ELtE/UB7eqwa6ALOADTc9w5ILonUcLWcwUMgseWIdmSORCDFV1A819VxZKC7bsfkoF9BJH7y
X-Received: by 10.99.178.6 with SMTP id x6mr22778914pge.98.1520547433532;
        Thu, 08 Mar 2018 14:17:13 -0800 (PST)
ARC-Seal: i=1; a=rsa-sha256; t=1520547433; cv=none;
        d=google.com; s=arc-20160816;
        b=0SzB9xtRhSS1D6ejlrGRds2j3hl3TyFE8n3LEDZ3KOtrdpn+tJvTI05qthF6G/YRSI
         rZx0MtHty5nqTeHjHjCVULo7aKoKtV3wBOCMk/oC+x9Mhym1mbMd7I7NAPm4CIO0rGVA
         8zQ97Eq6/hqSsNqYx8Xm9MQOeMKkZwMevKPamkRboXK4vO8RFeCTKHSFKLLWMi7lscwS
         hPlmZ++W6QcpyHBAQeYBk1mfEDKsyb7kLWKoOA98EP4W7fSvLE1HeEfRtQw9Hb6F2ZSy
         7IMcG8p9/2wb1HJxr67ExkvKaGub9K657DYzry5vx1ch5/lbOnebunwJB57tj2JiF7RW
         XEdQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:content-transfer-encoding
         :content-language:in-reply-to:mime-version:user-agent:date
         :message-id:from:references:to:subject:arc-authentication-results;
        bh=MpKYPAB4HASS7X8gnAQPgIT4dUaM0nTC8Uic2iy9J/Y=;
        b=H83Adjbq6n2KW4kPMzsJOKlte6VMZG0IW3nrAHtalW4u5HQKLAj5g4QGa+/V9sUjVw
         t7WvmIHKQeMgTty3FEKhbUmurb/DHZu6GA9Pz6pGfWRFD/0LnuYi8PZFqxDxuokcH/uy
         UijQ0iKKGELu7RsphUPPC22bmfKEcNhYH4vq+4BW3jEfBSl6foZfGdywOx5Rr0Zk3YXH
         RJgPjlaFwWDWshMjyjqppYWcbmTTOT4bRHA+fiI1CXYXglRJ0EY22Fh+h2r2gc7ZZmpi
         DhZ4432Coq0N7tPy9q4SlVNe6wtqtck3jgpdWX/28nOXJFg7CafrYzGh7qDLQeXmtv9l
         y5qg==
ARC-Authentication-Results: i=1; mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id n9si13533435pgq.187.2018.03.08.14.16.59;
        Thu, 08 Mar 2018 14:17:13 -0800 (PST)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1751136AbeCHWP7 (ORCPT <rfc822;arandomawesomegeek@gmail.com>
        + 99 others); Thu, 8 Mar 2018 17:15:59 -0500
Received: from hqemgate14.nvidia.com ([216.228.121.143]:10727 "EHLO
        hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1751073AbeCHWP4 (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Thu, 8 Mar 2018 17:15:56 -0500
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com
        id <B5aa1b6100000>; Thu, 08 Mar 2018 14:15:44 -0800
Received: from HQMAIL105.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Thu, 08 Mar 2018 14:15:55 -0800
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Thu, 08 Mar 2018 14:15:55 -0800
Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL105.nvidia.com
 (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Mar
 2018 22:15:54 +0000
Received: from [10.26.11.23] (10.26.11.23) by UKMAIL101.nvidia.com
 (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Mar
 2018 22:15:51 +0000
Subject: Re: [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs
To:     Peter De Schrijver <pdeschrijver@nvidia.com>,
        <linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <mturquette@baylibre.com>, <sboyd@codeaurora.org>,
        <robh+dt@kernel.org>, <mark.rutland@arm.com>,
        <devicetree@vger.kernel.org>, <lgirdwood@gmail.com>,
        <broonie@kernel.org>, <linux-kernel@vger.kernel.org>
References: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com>
 <1517934852-23255-4-git-send-email-pdeschrijver@nvidia.com>
From:   Jon Hunter <jonathanh@nvidia.com>
Message-ID: <80ee8493-6741-43dd-691a-eade94ec924f@nvidia.com>
Date:   Thu, 8 Mar 2018 22:15:51 +0000
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101
 Thunderbird/52.6.0
MIME-Version: 1.0
In-Reply-To: <1517934852-23255-4-git-send-email-pdeschrijver@nvidia.com>
X-Originating-IP: [10.26.11.23]
X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com
 (10.26.138.13)
Content-Type: text/plain; charset="utf-8"
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


On 06/02/18 16:34, Peter De Schrijver wrote:
> In a future patch, support for the DFLL in Tegra210 will be introduced.
> This requires support for more than 1 set of CVB and CPU max frequency
> tables.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 37 ++++++++++++++++++++++++------
>  1 file changed, 30 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> index e2dbb79..6486ad9 100644
> --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> @@ -21,6 +21,7 @@
>  #include <linux/err.h>
>  #include <linux/kernel.h>
>  #include <linux/init.h>
> +#include <linux/of_device.h>
>  #include <linux/platform_device.h>
>  #include <linux/regulator/consumer.h>
>  #include <soc/tegra/fuse.h>
> @@ -29,8 +30,15 @@
>  #include "clk-dfll.h"
>  #include "cvb.h"
>  
> +struct dfll_fcpu_data {
> +	const unsigned long *cpu_max_freq_table;
> +	unsigned int cpu_max_freq_table_size;
> +	const struct cvb_table *cpu_cvb_tables;
> +	unsigned int cpu_cvb_tables_size;
> +};
> +
>  /* Maximum CPU frequency, indexed by CPU speedo id */
> -static const unsigned long cpu_max_freq_table[] = {
> +static const unsigned long tegra124_cpu_max_freq_table[] = {
>  	[0] = 2014500000UL,
>  	[1] = 2320500000UL,
>  	[2] = 2116500000UL,
> @@ -80,6 +88,21 @@
>  	},
>  };
>  
> +static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
> +	.cpu_max_freq_table = tegra124_cpu_max_freq_table,
> +	.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
> +	.cpu_cvb_tables = tegra124_cpu_cvb_tables,
> +	.cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
> +};
> +
> +static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
> +	{
> +		.compatible = "nvidia,tegra124-dfll",
> +		.data = &tegra124_dfll_fcpu_data,
> +	},
> +	{ },
> +};
> +
>  static int get_alignment_from_regulator(struct device *dev,
>  					struct rail_alignment *align)
>  {
> @@ -112,12 +135,17 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
>  {
>  	int process_id, speedo_id, speedo_value, err;
>  	struct tegra_dfll_soc_data *soc;
> +	const struct of_device_id *of_id;
> +	const struct dfll_fcpu_data *fcpu_data;
> +
> +	of_id = of_match_device(tegra124_dfll_fcpu_of_match, &pdev->dev);
> +	fcpu_data = of_id->data;

Nit-pick, we can use of_device_get_match_data() here.


>  	process_id = tegra_sku_info.cpu_process_id;
>  	speedo_id = tegra_sku_info.cpu_speedo_id;
>  	speedo_value = tegra_sku_info.cpu_speedo_value;
>  
> -	if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) {
> +	if (speedo_id >= fcpu_data->cpu_max_freq_table_size) {
>  		dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
>  			speedo_id);
>  		return -ENODEV;
> @@ -172,11 +200,6 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
> -	{ .compatible = "nvidia,tegra124-dfll", },
> -	{ },
> -};
> -
>  static const struct dev_pm_ops tegra124_dfll_pm_ops = {
>  	SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
>  			   tegra_dfll_runtime_resume, NULL)
> 

Otherwise ...

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic