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[209.132.180.67]) by mx.google.com with ESMTP id g1si13476837pgc.726.2018.03.08.15.23.26; Thu, 08 Mar 2018 15:23:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751263AbeCHXWT (ORCPT + 99 others); Thu, 8 Mar 2018 18:22:19 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13664 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751238AbeCHXWQ (ORCPT ); Thu, 8 Mar 2018 18:22:16 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 08 Mar 2018 15:22:14 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 08 Mar 2018 15:22:15 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 08 Mar 2018 15:22:15 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Mar 2018 23:22:14 +0000 Received: from [10.26.11.23] (10.26.11.23) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Mar 2018 23:22:11 +0000 Subject: Re: [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210 To: Peter De Schrijver , , , , , , , , , , References: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com> <1517934852-23255-9-git-send-email-pdeschrijver@nvidia.com> From: Jon Hunter Message-ID: <6ea88ecd-20bb-31f6-74ad-7f7e3aaecfe1@nvidia.com> Date: Thu, 8 Mar 2018 23:22:09 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1517934852-23255-9-git-send-email-pdeschrijver@nvidia.com> X-Originating-IP: [10.26.11.23] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/02/18 16:34, Peter De Schrijver wrote: > Tegra210 has a DFLL as well and can share the majority of the code with > the Tegra124 implementation. So build the same code for both platforms. > > Signed-off-by: Peter De Schrijver > --- > drivers/clk/tegra/Kconfig | 5 +++++ > drivers/clk/tegra/Makefile | 2 +- > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig > index 7ddacae..57902ab 100644 > --- a/drivers/clk/tegra/Kconfig > +++ b/drivers/clk/tegra/Kconfig > @@ -5,3 +5,8 @@ config TEGRA_CLK_EMC > config CLK_TEGRA_BPMP > def_bool y > depends on TEGRA_BPMP > + > +config TEGRA_CLK_DFLL > + depends on (ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC) > + select PM_OPP > + def_bool y > diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile > index b716923..fc7f4b4 100644 > --- a/drivers/clk/tegra/Makefile > +++ b/drivers/clk/tegra/Makefile > @@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o > obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o > obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o > obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o > -obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o > +obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o > obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o > obj-y += cvb.o > obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o > Reviewed-by: Jon Hunter Cheers Jon -- nvpublic