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[209.132.180.67]) by mx.google.com with ESMTP id l67si16450402pfb.329.2018.03.08.15.26.27; Thu, 08 Mar 2018 15:26:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751483AbeCHXZL (ORCPT + 99 others); Thu, 8 Mar 2018 18:25:11 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13689 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750930AbeCHXZJ (ORCPT ); Thu, 8 Mar 2018 18:25:09 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 08 Mar 2018 15:24:57 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 08 Mar 2018 15:25:07 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 08 Mar 2018 15:25:07 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Mar 2018 23:25:08 +0000 Received: from [10.26.11.23] (10.26.11.23) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Mar 2018 23:25:04 +0000 Subject: Re: [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 To: Peter De Schrijver , , , , , , , , , , References: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com> <1517934852-23255-10-git-send-email-pdeschrijver@nvidia.com> From: Jon Hunter Message-ID: Date: Thu, 8 Mar 2018 23:25:04 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1517934852-23255-10-git-send-email-pdeschrijver@nvidia.com> X-Originating-IP: [10.26.11.23] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/02/18 16:34, Peter De Schrijver wrote: > Tegra210 has a very similar CPU clocking scheme than Tegra124. So add > support in this driver. Also allow for the case where the CPU voltage is > controlled directly by the DFLL rather than by a separate regulator object. > > Signed-off-by: Peter De Schrijver > --- > drivers/cpufreq/tegra124-cpufreq.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c > index 4353025..f8e01a8 100644 > --- a/drivers/cpufreq/tegra124-cpufreq.c > +++ b/drivers/cpufreq/tegra124-cpufreq.c > @@ -64,7 +64,8 @@ static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv) > { > clk_set_parent(priv->cpu_clk, priv->pllp_clk); > clk_disable_unprepare(priv->dfll_clk); > - regulator_sync_voltage(priv->vdd_cpu_reg); > + if (priv->vdd_cpu_reg) > + regulator_sync_voltage(priv->vdd_cpu_reg); > clk_set_parent(priv->cpu_clk, priv->pllx_clk); > } > > @@ -89,10 +90,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) > return -ENODEV; > > priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu"); > - if (IS_ERR(priv->vdd_cpu_reg)) { > - ret = PTR_ERR(priv->vdd_cpu_reg); > - goto out_put_np; > - } > + if (IS_ERR(priv->vdd_cpu_reg) != -EPROBE_DEFER) > + priv->vdd_cpu_reg = NULL; > + else > + return -EPROBE_DEFER; I am still not sure that we should rely on the fact that the regulator is not present in DT to imply that we do not need it. I think that we should be checking if we are using I2C mode here. Cheers Jon -- nvpublic