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[209.132.180.67]) by mx.google.com with ESMTP id d2si445959pge.465.2018.03.09.00.57.31; Fri, 09 Mar 2018 00:57:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=m26eIQsL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932096AbeCIIy6 (ORCPT + 99 others); Fri, 9 Mar 2018 03:54:58 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:62753 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750920AbeCIIyy (ORCPT ); Fri, 9 Mar 2018 03:54:54 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w298s50H016976; Fri, 9 Mar 2018 02:54:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1520585645; bh=+Xd91LbRmB6AFzhVe7bF344lLuANhGPItFO7f62KkfA=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=m26eIQsLLEcPh4SCGkJqZWyQH5tfl2D+0rNy8SG0joiDJMTkZrOelFKrNNPudQ79U Vx5gOBL9r0hIMgqXCKno1vGIs+ACX9mImoHvZhkmacf2h8e551EZgzDLwGQaKMT3x1 P9eASD9971B3pCyNrnkI5Ogsolcg7GBBWmGTzY/M= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w298s47f015686; Fri, 9 Mar 2018 02:54:05 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 9 Mar 2018 02:54:04 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 9 Mar 2018 02:54:04 -0600 Received: from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w298s0n1015767; Fri, 9 Mar 2018 02:54:01 -0600 Subject: Re: [PATCH] usb: dwc3: core: power on PHYs before initializing core To: Brian Norris , Felipe Balbi CC: William Wu , , , , , , , , , , , , , References: <1515729616-8639-1-git-send-email-william.wu@rock-chips.com> <87ina6vodf.fsf@linux.intel.com> <20180308164916.GA65031@rodete-desktop-imager.corp.google.com> From: Roger Quadros Message-ID: Date: Fri, 9 Mar 2018 10:54:00 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180308164916.GA65031@rodete-desktop-imager.corp.google.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-GB Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 08/03/18 18:49, Brian Norris wrote: > Hi, > > On Thu, Mar 08, 2018 at 12:43:40PM +0200, Felipe Balbi wrote: >> William Wu writes: >>> The dwc3_core_init() gets the PHYs and initializes the PHYs with >>> the usb_phy_init() and phy_init() functions before initializing >>> core, and power on the PHYs after core initialization is done. >>> >>> However, some platforms (e.g. Rockchip RK3399 DWC3 with Type-C >>> USB3 PHY), it needs to do some special operation while power on >>> the Type-C PHY before initializing DWC3 core. It's because that >>> the RK3399 Type-C PHY requires to hold the DWC3 controller in >>> reset state to keep the PIPE power state in P2 while configuring >>> the Type-C PHY, otherwise, it may cause waiting for the PIPE ready >>> timeout. In this case, if we power on the PHYs after the DWC3 core >>> initialization is done, the core will be reset to uninitialized >>> state after power on the PHYs. >>> >>> Fix this by powering on the PHYs before initializing core. And >>> because the GUID register may also be reset in this case, so we >>> need to configure the GUID register after powering on the PHYs. >>> >>> Signed-off-by: William Wu >> >> does this cause any regressions for your boards? > > I'm not Roger, but I believe it was determined we don't need this for > the Rockchip systems for which William was originally sending this. At > least not right now. I believe our PHY init problems were mostly > resolved in other ways. > > (Although I hear USB is currently pretty broken around suspend/resume > for us on -next. Likely unrelated.) > > I guess we never clearly replied stating the above. I hope this isn't > merged anywhere? Or I guess it's no problem to me at the moment, but it > might be needless churn. > I did some quick tests on TI platforms and didn't see any issues with this patch. Since this patch isn't really fixing your problem and we didn't have any problems to start with I'd suggest to avoid this churn for now. -- cheers, -roger Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki