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[209.132.180.67]) by mx.google.com with ESMTP id d71si451664pgc.411.2018.03.09.01.20.35; Fri, 09 Mar 2018 01:20:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XuRgwnz2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751182AbeCIJTo (ORCPT + 99 others); Fri, 9 Mar 2018 04:19:44 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:46695 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751101AbeCIJTm (ORCPT ); Fri, 9 Mar 2018 04:19:42 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w299Jer1008185; Fri, 9 Mar 2018 03:19:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1520587180; bh=h/3n4R0KYdUHfLF94dbkabagOvlEQhSDhEgHZ96U2X8=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=XuRgwnz26f6/DAvq8soQkHXLSkj0zKoY9gYjfPVo59Tk0IF9Cw1OVwTXUHEaR/Qf6 FK+kHPon4S2CKY+NwWEjyLTGJk0gq9nbSfrh1wQD5t/FHQOBmWDm4L/CzWp2U2F/fb R+HxmuH8KxiiXA0KfM7+MjjcAoBj730toH/JQU0Q= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w299JexE031494; Fri, 9 Mar 2018 03:19:40 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 9 Mar 2018 03:19:39 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 9 Mar 2018 03:19:39 -0600 Received: from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w299Jcv7031302; Fri, 9 Mar 2018 03:19:38 -0600 Subject: Re: [PATCH] usb: dwc3: Prevent indefinite sleep in _dwc3_set_mode during suspend/resume To: Felipe Balbi , Baolin Wang CC: USB , LKML References: <1519730526-22274-1-git-send-email-rogerq@ti.com> <87sh9l5z4l.fsf@linux.intel.com> <94cd6377-1327-2309-8d69-6ab0de2bdfd4@ti.com> <87po4i3o1v.fsf@linux.intel.com> <87k1uq3ho6.fsf@linux.intel.com> <8ec0485e-89af-568b-e34a-b0cd490817d0@ti.com> <87h8puwyn5.fsf@linux.intel.com> From: Roger Quadros Message-ID: <5bc56ef5-66b1-d40c-1639-e748fe18cdbd@ti.com> Date: Fri, 9 Mar 2018 11:19:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <87h8puwyn5.fsf@linux.intel.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-GB Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/03/18 13:27, Felipe Balbi wrote: > > Hi, > > Baolin Wang writes: >>>>>>>>>> void dwc3_gadget_exit(struct dwc3 *dwc) >>>>>>>>>> { >>>>>>>>>> + int epnum; >>>>>>>>>> + unsigned long flags; >>>>>>>>>> + >>>>>>>>>> + spin_lock_irqsave(&dwc->lock, flags); >>>>>>>>>> + for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { >>>>>>>>>> + struct dwc3_ep *dep = dwc->eps[epnum]; >>>>>>>>>> + >>>>>>>>>> + if (!dep) >>>>>>>>>> + continue; >>>>>>>>>> + >>>>>>>>>> + dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; >>>>>>>>>> + } >>>>>>>>>> + spin_unlock_irqrestore(&dwc->lock, flags); >>>>>>>>>> + >>>>>>>>>> usb_del_gadget_udc(&dwc->gadget); >>>>>>>>>> dwc3_gadget_free_endpoints(dwc); >>>>>>>>> >>>>>>>>> free endpoints is a better place for this. It's already going to free >>>>>>>>> the memory anyway. Might as well clear all flags to 0 there. >>>>>>>>> >>>>>>>> >>>>>>>> But it won't solve the deadlock issue. Since dwc3_gadget_free_endpoints() >>>>>>>> is called after usb_del_gadget_udc() and the deadlock happens when >>>>>>>> >>>>>>>> usb_del_gadget_udc()->udc_stop()->dwc3_gadget_stop()->wait_event_lock_irq() >>>>>>>> >>>>>>>> and DWC3_EP_END_TRANSFER_PENDING flag is set. >>>>>>> >>>>>>> indeed. Iterating twice over the entire endpoint list seems >>>>>>> wasteful. Perhaps we just shouldn't wait when removing the UDC since >>>>>>> that's essentially what this patch will do, right? If you clear the flag >>>>>>> before calling ->udc_stop(), this means the loop in dwc3_gadget_stop() >>>>>>> will do nothing. Might as well remove it. >>>>>>> >>>>>> >>>>>> This means that we will never wait for DWC3_EP_END_TRANSFER_PENDING to clear >>>>>> in dwc3_gadget_stop() like we used to. This is perfectly fine, right? >>>>>> >>>>>> It makes sense to me as dwc3_gadget_stop() calls __dwc3_gadget_stop() which >>>>>> masks all interrupts and nobody will ever clear that flag if it was set. >>>>> >>>>> I don't think so. It can not mask the endpoint events, please check >>>>> the events which will be masked in DEVTEN register. The reason why we >>>>> should wait for DWC3_EP_END_TRANSFER_PENDING to clear is that, >>>>> sometimes the DWC3_DEPEVT_EPCMDCMPLT event will be triggered later >>>>> than 100us, but now we may have freed the gadget irq which will cause >>>>> crash. >>>> >>>> We could mask command complete events as soon as ->udc_stop() is called, >>>> right? Hmm, actually, __dwc3_gadget_stop() already clears DEVTEN >>>> completely. >>> >>> But which bit in DEVTEN says Endpoint events are disabled? >> >> When we set up the DWC3_DEPCMD_ENDTRANSFER command in >> dwc3_stop_active_transfer(), we can do not set DWC3_DEPCMD_CMDIOC, >> then there will no endpoint command complete interrupts I think. >> >> cmd |= DWC3_DEPCMD_CMDIOC; > > I remember some part of the databook mandating CMDIOC to be set. We > could test it out without and see if anything blows up. I would, > however, require a lengthy comment explaining that we're deviating from > databook revision x.yya, section foobar because $reasons. :-) > This is what the v3.10 databook says "When issuing an End Transfer command, software must set the CmdIOC bit (field 8) so that an Endpoint Command Complete event is generated after the transfer ends. This is necessary to synchronize the conclusion of system bus traffic before the End Transfer command is completed." with a note "If GUCTL2[Rst_actbitlater] is set, Software can poll the completion of the End Transfer command by polling the command active bit to be cleared to 0." fyi. Rst_actbitlater - "Enable clearing of the command active bit for the ENDXFER command after the command execution is completed. This bit is valid in device mode only." So I'd prefer not to clear CMDIOC for all cases. Could we some how just tackle the dwc3_gadget_exit case like I did in this patch? -- cheers, -roger Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki