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[209.132.180.67]) by mx.google.com with ESMTP id z22si530163pgc.398.2018.03.09.02.22.08; Fri, 09 Mar 2018 02:22:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751512AbeCIKUo (ORCPT + 99 others); Fri, 9 Mar 2018 05:20:44 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:40898 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbeCIKU3 (ORCPT ); Fri, 9 Mar 2018 05:20:29 -0500 Received: from hsi-kbw-5-158-153-52.hsi19.kabel-badenwuerttemberg.de ([5.158.153.52] helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1euF8H-0006IZ-EH; Fri, 09 Mar 2018 11:20:13 +0100 Date: Fri, 9 Mar 2018 11:20:12 +0100 (CET) From: Thomas Gleixner To: Palmer Dabbelt cc: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, LAK , LKML , openrisc@lists.librecores.org, linux-riscv@lists.infradead.org, Russell King Subject: Re: Make set_handle_irq and handle_arch_irq generic, v3 In-Reply-To: <20180307235731.22627-1-palmer@sifive.com> Message-ID: References: <20180307235731.22627-1-palmer@sifive.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 7 Mar 2018, Palmer Dabbelt wrote: > This is my third version of this patch set, but the original cover > letter is still the most relevant description I can come up with. > > This patch set has been sitting around for a while, but it got a bit lost > in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry > point for interrupt handling) to our first-level interrupt controller. > While this isn't completely crazy (as the first-level interrupt controller > is specified by the ISA), it is a bit awkward. > > This patch set decouples our trap handler from our first-level IRQ chip > driver by copying what a handful of other architectures are doing. This > does add an additional load to the interrupt handling path, but there's a > handful of performance problems in there that I've been meaning to look at > so I don't mind adding another one for now. The advantage is that our > irqchip driver is decoupled from our arch port, at least at compile time. > > I've build tested this with defconfigs on all the modified architectures > after both patch 1 and 5. I've left the old acks in for the later > patches as the patch set has changed very little since I last submitted > it. This looks sensible. We have two options for getting this merged: 1) I'll take the whole lot through tip/irq/core 2) I'll apply patch 1/N to a special branch in tip. That branch will contain only this commit on top of 4.16-rc4 and can be pulled by the relevant architecture maintainers, so they can apply their architecture specific patches. Please let me know how you want to proceed. Thanks, tglx