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([2a01:e35:879a:6cd0:3e97:eff:fe5b:1402]) by smtp.googlemail.com with ESMTPSA id j89sm1105218wrj.92.2018.03.09.05.25.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 05:25:04 -0800 (PST) Subject: Re: [PATCH v5 2/2] clocksource/drivers/npcm: Add NPCM7xx timer driver To: Tomer Maimon Cc: Rob Herring , Mark Rutland , Thomas Gleixner , Avi Fishman , Brendan Higgins , venture@google.com, Joel Stanley , devicetree , Linux Kernel Mailing List , OpenBMC Maillist References: <1520522698-16153-1-git-send-email-tmaimon77@gmail.com> <1520522698-16153-3-git-send-email-tmaimon77@gmail.com> <2a83eb83-10a9-54f3-e0da-bd6cf32b5ac1@linaro.org> From: Daniel Lezcano Message-ID: Date: Fri, 9 Mar 2018 14:25:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/03/2018 23:37, Tomer Maimon wrote: > On 8 March 2018 at 17:33, Daniel Lezcano wrote: >> On 08/03/2018 16:24, Tomer Maimon wrote: >>> Add Nuvoton BMC NPCM7xx timer driver. >>> >>> The clocksource Enable 24-bit TIMER0 and TIMER1 counters, >>> while TIMER0 serve as clockevent and TIMER1 serve as clocksource. >>> >>> Signed-off-by: Tomer Maimon >>> Reviewed-by: Brendan Higgins >>> --- >> >> [ ... ] >> >>> + >>> + pr_info("Enabling NPCM7xx clocksource timer base: 0x%x, IRQ: %d ", >>> + (int)timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to)); >> >> You can use '%p' instead of '0x%x' and remove the (int) cast. > I think we need to use in the pr_info %px, if I use %p I get in the > kernel boot print "(ptrval)" instead of the address. > please refer: https://lwn.net/Articles/740249/ Ah yes, right. Thanks -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog