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Date:   Fri, 9 Mar 2018 13:47:59 +0000
From:   Will Deacon <will.deacon@arm.com>
To:     Mark Rutland <mark.rutland@arm.com>
Cc:     Shanker Donthineni <shankerd@codeaurora.org>,
        Robin Murphy <robin.murphy@arm.com>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        kvmarm <kvmarm@lists.cs.columbia.edu>,
        Marc Zyngier <marc.zyngier@arm.com>,
        Vikram Sethi <vikrams@codeaurora.org>,
        Philip Elcan <pelcan@codeaurora.org>
Subject: Re: [PATCH v7] arm64: Add support for new control bits CTR_EL0.DIC
 and CTR_EL0.IDC
Message-ID: <20180309134759.GB15537@arm.com>
References: <1520434808-29703-1-git-send-email-shankerd@codeaurora.org>
 <20180309134439.76b43chxnrw7okrw@lakrids.cambridge.arm.com>
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On Fri, Mar 09, 2018 at 01:44:40PM +0000, Mark Rutland wrote:
> On Wed, Mar 07, 2018 at 09:00:08AM -0600, Shanker Donthineni wrote:
> >  static inline void __flush_icache_all(void)
> >  {
> > -	asm("ic	ialluis");
> > -	dsb(ish);
> > +	/* Instruction cache invalidation is not required for I/D coherence? */
> > +	if (!cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) {
> > +		asm("ic	ialluis");
> > +		dsb(ish);
> > +	}
> >  }
> 
> I don't think we need the comment here. We don't have this in the other
> cases we look at the ARM64_HAS_CACHE_{IDC,DIC} caps.
> 
> This would also be slightly nicer as an early return:
> 
> static inline void __flush_icache_all(void)
> {
> 	if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))
> 		return;
> 	
> 	asm("ic ialluis");
> 	dsb(ish);
> }
> 
> ... which minimizes indentation, and the diffstat.
> 
> The rest looks fine to me, so with the above changes:
> 
> Reviewed-by: Mark Rutland <mark.rutland@arm.com>

I've already queued this, but not pushed out yet so I'll fold these changes
in.

Will