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[209.132.180.67]) by mx.google.com with ESMTP id 37-v6si1223465ple.599.2018.03.09.09.57.33; Fri, 09 Mar 2018 09:57:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=UXefbiFb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932384AbeCIR4W (ORCPT + 99 others); Fri, 9 Mar 2018 12:56:22 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:42446 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751205AbeCIR4V (ORCPT ); Fri, 9 Mar 2018 12:56:21 -0500 Received: by mail-pg0-f65.google.com with SMTP id y8so3815534pgr.9 for ; Fri, 09 Mar 2018 09:56:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=date:subject:in-reply-to:cc:from:to:message-id:mime-version :content-transfer-encoding; bh=zjHZK+a/Ne/S5jTRiuu9vrY3SvMyUeppDsOjQYHZQ58=; b=UXefbiFbe84u5WzO03KpvvYxGO7DCZb0o8jBwm+qItcaS3NL2T7dI7CQWpPKdns13v MRHCb8dYSsy4nifNAvSq4THOEANMoOIpVfazz9sBudj8SJjTz43l5v0aUYWPq1FyiWWp rqgYQNaxwI4x8W8DPcpf/oNgVPZOE7WPIRJgqFaz6PR7zDzgSOHtsvjcY2G/JHn5QYbt qTLb8JK8MP6bpHLcvwpJw14udyqwO12EPkF/JXBHONAkcef6Im2JZUmclq4P2quThFN9 E7LEzSnpOPiP9FWZ/oBFdVbunipRvIJ+d68wNeitTBJAotNAUI63jdXKMSVhTDOQQ0Qk mn+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=zjHZK+a/Ne/S5jTRiuu9vrY3SvMyUeppDsOjQYHZQ58=; b=St9QinwkRwdhoyeM16FzGS8AoK9MgBKS8bIClwbK1vYS+PrFhnXXVQ0yi1QoLHzi0s NrhH6/o9ysd/FHI+I4Jb+l6rIbtExWyIaLUC+k7dPJn3XOfqN1jPsbGzIGmyaPoiDfHU B4/hyp8EuXazn75998BOjyd2IjvXvdvrH/d8NINxbPTXvjOo1rHI9k0mv2SpR/06i1ZA FSt9kclW9kUcGqSDe1H2uR/PkisxNeRcTOH26lWjSKEnsmmlBsb3dBFWf4uc543Ab2ZK 4xzWCNhPgZXS0z/+wVc8u1WA3BZaCkKZ4ai6nBRZUzeNqAlKjKpLqNCN/Xe+lXAjrOqw JCog== X-Gm-Message-State: APf1xPAzryeW3k5GBtkcrjS9V5Tk7WvTgUuwJhKUasFyp3Q59OOl35Tg rbJBldpqet9OTLXKwO83V8JexQ== X-Received: by 10.98.160.142 with SMTP id p14mr31261595pfl.134.1520618180676; Fri, 09 Mar 2018 09:56:20 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id p16sm4305092pfd.77.2018.03.09.09.56.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 09:56:20 -0800 (PST) Date: Fri, 09 Mar 2018 09:56:20 -0800 (PST) X-Google-Original-Date: Fri, 09 Mar 2018 09:12:16 PST (-0800) Subject: Re: Make set_handle_irq and handle_arch_irq generic, v3 In-Reply-To: CC: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openrisc@lists.librecores.org, linux-riscv@lists.infradead.org, linux@arm.linux.org.uk From: Palmer Dabbelt To: tglx@linutronix.de Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 09 Mar 2018 02:20:12 PST (-0800), tglx@linutronix.de wrote: > On Wed, 7 Mar 2018, Palmer Dabbelt wrote: > >> This is my third version of this patch set, but the original cover >> letter is still the most relevant description I can come up with. >> >> This patch set has been sitting around for a while, but it got a bit lost >> in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry >> point for interrupt handling) to our first-level interrupt controller. >> While this isn't completely crazy (as the first-level interrupt controller >> is specified by the ISA), it is a bit awkward. >> >> This patch set decouples our trap handler from our first-level IRQ chip >> driver by copying what a handful of other architectures are doing. This >> does add an additional load to the interrupt handling path, but there's a >> handful of performance problems in there that I've been meaning to look at >> so I don't mind adding another one for now. The advantage is that our >> irqchip driver is decoupled from our arch port, at least at compile time. >> >> I've build tested this with defconfigs on all the modified architectures >> after both patch 1 and 5. I've left the old acks in for the later >> patches as the patch set has changed very little since I last submitted >> it. > > This looks sensible. We have two options for getting this merged: > > 1) I'll take the whole lot through tip/irq/core > > 2) I'll apply patch 1/N to a special branch in tip. That branch will contain > only this commit on top of 4.16-rc4 and can be pulled by the relevant > architecture maintainers, so they can apply their architecture specific > patches. Option 1 seems like the lowest overhead, as that way we don't need to sequence the patches between multiple trees. If all the other arch maintianers are OK with it then that works for me. The 0-day robot found a new build warning on openrisc. I was plannning on submitting a v4 with this fix in it diff --git a/arch/openrisc/include/asm/irq.h b/arch/openrisc/include/asm/irq.h index d9eee0a2b7b4..eb612b1865d2 100644 --- a/arch/openrisc/include/asm/irq.h +++ b/arch/openrisc/include/asm/irq.h @@ -24,6 +24,4 @@ #define NO_IRQ (-1) -extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); - #endif /* __ASM_OPENRISC_IRQ_H__ */ I can submit a v4, or you can just grab it from https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/log/?h=review-irq-1-cleanup Thanks!