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[209.132.180.67]) by mx.google.com with ESMTP id e2si1069718pga.394.2018.03.09.10.45.20; Fri, 09 Mar 2018 10:45:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=duVZ6jqx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932635AbeCISnk (ORCPT + 99 others); Fri, 9 Mar 2018 13:43:40 -0500 Received: from mail-yw0-f193.google.com ([209.85.161.193]:37646 "EHLO mail-yw0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932195AbeCISni (ORCPT ); Fri, 9 Mar 2018 13:43:38 -0500 Received: by mail-yw0-f193.google.com with SMTP id j143so1503634ywb.4; Fri, 09 Mar 2018 10:43:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GROmPBxV+GD1tqD4eZDPDr33GGevKBJSyke88+D+PtE=; b=duVZ6jqxpxekbi3e7nqVnIlp/UKWrukWCB/1cE0f3hwQOPsd/VXOSzJK/urdRpZ3Oq t36xTxiEeDhCubylH+6fuW4/2UHGBQ42S+UDooE5+rPjxywVRrsqY0wZ2hGS5t7JW34C BoUzqy1SVnjiZHuTMMFODDqXd+9ovsDmEC/PT5zpMVCk05AMJ15YZKn9F/E0O1n113p+ NiJwKxurU/ITkQ6kgMHxaCoKvQf6t2ogwlX+CAziZA+q1N4ZdJqCmd4xPdQAcxxDHWPU 1SKpk5WaGWr5qZFE6WwHRUxgGEUwEBJIAkPmbOq1RD1M5weqSVY5LplKSYuPWGRZh+Q1 YwEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GROmPBxV+GD1tqD4eZDPDr33GGevKBJSyke88+D+PtE=; b=sNdhWnk4qtvjNZ+usjliCszVYHnMrPrDVST19Oo5460WSyFzVf3aP9HQQTfch1gymZ A+VgB1YO3QWBejElP6OG528pDLJSjzHNLJbv0xEQqdPbPIjONju9DcZt748NAtYH+L/6 vMY5c5IhKKBzg4R8oxhv+RLxD8m02Pu9sGUxcHU15TgVOO1nY9FskzL1Ap4UhU9DYfFf HLq9fXj+WXF8MsG0zepxyd5m4RfTARC9AWjcPr0/f/qWznST/WPtordZlOy436iNWtQn vSMWDaXjLbARPFBYHX0OS+tx/ZnSv9rfi83jvvxrlIQClOa95Q/GiyqSq3IVGs6WZcnu PPdw== X-Gm-Message-State: APf1xPCC33jR6ZisHNbZ70BYF8IgcqvzmLHPPtGJFyyWgpAobB8WR6iJ vEMx8by0UN9C5w1K/SZ9e4Y= X-Received: by 10.129.114.195 with SMTP id n186mr20390990ywc.149.1520621018079; Fri, 09 Mar 2018 10:43:38 -0800 (PST) Received: from localhost ([72.188.97.40]) by smtp.gmail.com with ESMTPSA id u128sm561974ywb.62.2018.03.09.10.43.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 10:43:37 -0800 (PST) From: William Breathitt Gray To: jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net Cc: benjamin.gaignard@st.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH v5 6/8] dt-bindings: counter: Document stm32 quadrature encoder Date: Fri, 9 Mar 2018 13:43:32 -0500 Message-Id: <7f160c33e6e37c13974054f3dcfea4a02f1250fb.1520614431.git.vilhelm.gray@gmail.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard Add bindings for STM32 Timer quadrature encoder. It is a sub-node of STM32 Timer which implement the counter part of the hardware. Signed-off-by: Benjamin Gaignard Signed-off-by: William Breathitt Gray --- .../bindings/counter/stm32-timer-cnt.txt | 26 ++++++++++++++++++++++ .../devicetree/bindings/mfd/stm32-timers.txt | 7 ++++++ 2 files changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt diff --git a/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt new file mode 100644 index 000000000000..377728128bef --- /dev/null +++ b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt @@ -0,0 +1,26 @@ +STMicroelectronics STM32 Timer quadrature encoder + +STM32 Timer provides quadrature encoder counter mode to detect +angular position and direction of rotary elements, +from IN1 and IN2 input signals. + +Must be a sub-node of an STM32 Timer device tree node. +See ../mfd/stm32-timers.txt for details about the parent node. + +Required properties: +- compatible: Must be "st,stm32-timer-counter". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes, + to set IN1/IN2 pins in mode of operation for Low-Power + Timer input on external pin. + +Example: + timers@40010000 { + compatible = "st,stm32-timers"; + ... + counter { + compatible = "st,stm32-timer-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&tim1_in_pins>; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt index 1db6e0057a63..ff9c14ada30b 100644 --- a/Documentation/devicetree/bindings/mfd/stm32-timers.txt +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt @@ -23,6 +23,7 @@ Optional parameters: Optional subnodes: - pwm: See ../pwm/pwm-stm32.txt - timer: See ../iio/timer/stm32-timer-trigger.txt +- counter: See ../counter/stm32-timer-cnt.txt Example: timers@40010000 { @@ -43,4 +44,10 @@ Example: compatible = "st,stm32-timer-trigger"; reg = <0>; }; + + counter { + compatible = "st,stm32-timer-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&tim1_in_pins>; + }; }; -- 2.16.2