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[209.132.180.67]) by mx.google.com with ESMTP id v145si1269077pgb.569.2018.03.09.13.13.33; Fri, 09 Mar 2018 13:13:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WdZnnjgs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932709AbeCIVKQ (ORCPT + 99 others); Fri, 9 Mar 2018 16:10:16 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:56143 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932643AbeCIVKN (ORCPT ); Fri, 9 Mar 2018 16:10:13 -0500 Received: by mail-wm0-f65.google.com with SMTP id q83so6286567wme.5 for ; Fri, 09 Mar 2018 13:10:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8Mtk73RhEVmkzRrq3lZNX81k7l6xB6WNz4oCph8qn5U=; b=WdZnnjgsrvTQXK+VQiS+mvLN+x96DXLzbqUwIc0gftNfh0SVAeArMUX4RkEz1eHEec +bx7vaPV04gv3Qj2t42lApuFTtqUsMxFxfOmY2P3QDTlix7FOcSPjM2EAUkUWdQO/+Et nWFdTChEx5SpBkalDgj/oH3Jzpx1D9GzrWDng= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8Mtk73RhEVmkzRrq3lZNX81k7l6xB6WNz4oCph8qn5U=; b=i9FrdJiY+R6u/G2du7zxa3VSgGz40twSUvUzLi/q2tpqB2riwJCqWXhPj/F2fPSZRh vbmkTN6/e3Ah5ql1mwzUih7fgCkkmEanUAqDCsfBNC9Ke9ib/1A3DETRTlZZOPtpmgww /3oW7+6HZUtznloSKJx8I5v0mGtel7HOcHOvbwc6FI/eIZ9KK17mSsxGhMzyNyB/3ROo YZB1BxjxkUmuqK8MOz8rAG51hZ7u6WoHQfi8r+YLFYD0ilxj8Ut2gSgNhtTTTRdmS7+e NvKwTjEF5TdczGRNiOGPA/dFbgt+ZdItSJMKirkiqdq5AW5yqiXl58syxjHJYtTS9MTZ dvXw== X-Gm-Message-State: AElRT7EAdJ3XNT1s2oVUAsaCsuRf+Mtin9x+V9ornAhAduSIN2vggaxe 4kOoVSO8/DrxBFSp16VM27sxx2rQMVs= X-Received: by 10.28.130.9 with SMTP id e9mr148589wmd.161.1520629811838; Fri, 09 Mar 2018 13:10:11 -0800 (PST) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id g7sm1853118wrb.78.2018.03.09.13.10.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 13:10:07 -0800 (PST) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, davidai@quicinc.com, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v4 4/7] interconnect: qcom: Add RPM communication Date: Fri, 9 Mar 2018 23:09:55 +0200 Message-Id: <20180309210958.16672-5-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180309210958.16672-1-georgi.djakov@linaro.org> References: <20180309210958.16672-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On some Qualcomm SoCs, there is a remote processor, which controls some of the Network-On-Chip interconnect resources. Other CPUs express their needs by communicating with this processor. Add a driver to handle comminication with this remote processor. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/interconnect/qcom-smd.txt | 31 ++++++++ drivers/interconnect/qcom/Makefile | 1 + drivers/interconnect/qcom/smd-rpm.c | 90 ++++++++++++++++++++++ drivers/interconnect/qcom/smd-rpm.h | 15 ++++ 4 files changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-smd.txt create mode 100644 drivers/interconnect/qcom/Makefile create mode 100644 drivers/interconnect/qcom/smd-rpm.c create mode 100644 drivers/interconnect/qcom/smd-rpm.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom-smd.txt b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt new file mode 100644 index 000000000000..14e83ed7019b --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt @@ -0,0 +1,31 @@ +Qualcomm SMD-RPM interconnect driver binding +------------------------------------------------ +The RPM is a dedicated hardware engine for managing the shared +SoC resources in order to keep the lowest power profile. It +communicates with other hardware subsystems via shared memory +and accepts requests for various resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,interconnect-smd-rpm" + +Example: + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <0 168 1>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + interconnect-smd-rpm { + compatible = "qcom,interconnect-smd-rpm"; + }; + + }; + }; + }; diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile new file mode 100644 index 000000000000..095bdef1ee6e --- /dev/null +++ b/drivers/interconnect/qcom/Makefile @@ -0,0 +1 @@ +obj-y += smd-rpm.o diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c new file mode 100644 index 000000000000..0cf772f51642 --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RPM over SMD communication wrapper for interconects + * + * Copyright (C) 2018 Linaro Ltd + * Author: Georgi Djakov + */ + +#include +#include +#include +#include +#include +#include +#include "smd-rpm.h" + +#define RPM_KEY_BW 0x00007762 + +static struct qcom_icc_rpm { + struct qcom_smd_rpm *rpm; +} icc_rpm_smd; + +struct icc_rpm_smd_req { + __le32 key; + __le32 nbytes; + __le32 value; +}; + +bool qcom_icc_rpm_smd_available(void) +{ + if (!icc_rpm_smd.rpm) + return false; + + return true; +} + +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val) +{ + struct icc_rpm_smd_req req = { + .key = cpu_to_le32(RPM_KEY_BW), + .nbytes = cpu_to_le32(sizeof(u32)), + .value = cpu_to_le32(val), + }; + + return qcom_rpm_smd_write(icc_rpm_smd.rpm, ctx, rsc_type, id, &req, + sizeof(req)); +} +EXPORT_SYMBOL(qcom_icc_rpm_smd_send); + +static int qcom_icc_rpm_smd_probe(struct platform_device *pdev) +{ + icc_rpm_smd.rpm = dev_get_drvdata(pdev->dev.parent); + if (!icc_rpm_smd.rpm) { + dev_err(&pdev->dev, "unable to retrieve handle to RPM\n"); + return -ENODEV; + } + + return 0; +} + +static const struct of_device_id qcom_icc_rpm_smd_dt_match[] = { + { .compatible = "qcom,interconnect-smd-rpm", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, qcom_interconnect_rpm_smd_dt_match); + +static struct platform_driver qcom_interconnect_rpm_smd_driver = { + .driver = { + .name = "qcom-interconnect-smd-rpm", + .of_match_table = qcom_icc_rpm_smd_dt_match, + }, + .probe = qcom_icc_rpm_smd_probe, +}; + +static int __init rpm_smd_interconnect_init(void) +{ + return platform_driver_register(&qcom_interconnect_rpm_smd_driver); +} +subsys_initcall(rpm_smd_interconnect_init); + +static void __exit rpm_smd_interconnect_exit(void) +{ + platform_driver_unregister(&qcom_interconnect_rpm_smd_driver); +} +module_exit(rpm_smd_interconnect_exit) + +MODULE_AUTHOR("Georgi Djakov "); +MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/smd-rpm.h b/drivers/interconnect/qcom/smd-rpm.h new file mode 100644 index 000000000000..0f4a3da31cf6 --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov + */ + +#ifndef __LINUX_INTERCONNECT_QCOM_RPM_H +#define __LINUX_INTERCONNECT_QCOM_RPM_H + +#include + +bool qcom_icc_rpm_smd_available(void); +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); + +#endif