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[209.132.180.67]) by mx.google.com with ESMTP id 18si1502501pfj.366.2018.03.09.13.35.34; Fri, 09 Mar 2018 13:35:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=JmTAD5Dl; dkim=pass header.i=@codeaurora.org header.s=default header.b=JmTAD5Dl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932674AbeCIVdb (ORCPT + 99 others); Fri, 9 Mar 2018 16:33:31 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:41048 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932327AbeCIVd3 (ORCPT ); Fri, 9 Mar 2018 16:33:29 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9EFBF60721; Fri, 9 Mar 2018 21:33:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520631208; bh=usBcS5voEzES5IUeiO0M9TpraLKEJMiJ8cSe0+THAS0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=JmTAD5DlrTxUnR+kDcPgty4l6gHxKhoCdldP58wVG4gpahYMW9dhb2z+10SiW6vQS N29xd16X792haAMli6o2qrZ/6mdoGCB6YiDaCrxEEh/aCuQIGLAxdm7tEUZr2kn4FZ u0PMLkpcBSg0mCtFi6VeD5k/6xstfmru0gmL5ibk= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id EB332602A0; Fri, 9 Mar 2018 21:33:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520631208; bh=usBcS5voEzES5IUeiO0M9TpraLKEJMiJ8cSe0+THAS0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=JmTAD5DlrTxUnR+kDcPgty4l6gHxKhoCdldP58wVG4gpahYMW9dhb2z+10SiW6vQS N29xd16X792haAMli6o2qrZ/6mdoGCB6YiDaCrxEEh/aCuQIGLAxdm7tEUZr2kn4FZ u0PMLkpcBSg0mCtFi6VeD5k/6xstfmru0gmL5ibk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org EB332602A0 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org Date: Fri, 9 Mar 2018 14:33:27 -0700 From: Lina Iyer To: Stephen Boyd Cc: andy.gross@linaro.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, rnayak@codeaurora.org, bjorn.andersson@linaro.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 01/10] drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs Message-ID: <20180309213327.GA2806@codeaurora.org> References: <20180302164317.10554-1-ilina@codeaurora.org> <20180302164317.10554-2-ilina@codeaurora.org> <152036550693.218381.11708415467260101936@swboyd.mtv.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <152036550693.218381.11708415467260101936@swboyd.mtv.corp.google.com> User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stephen, I will address all the comments in the next spin of the patch. Here are some responses to the questions. On Tue, Mar 06 2018 at 12:45 -0700, Stephen Boyd wrote: >Quoting Lina Iyer (2018-03-02 08:43:08) [...] > +#include > >If the driver doesn't become tristate, this should become export.h >instead of module.h > MODULE_DEVICE_TABLE seems to need this. [...] >> + >> +static void write_tcs_reg_sync(struct rsc_drv *drv, int reg, int m, int n, >> + u32 data) >> +{ >> + write_tcs_reg(drv, reg, m, n, data); >> + for (;;) { >> + if (data == read_tcs_reg(drv, reg, m, n)) >> + break; >> + udelay(1); > >Hopefully this never gets stuck. Add a timeout? > No, it wont. The read is to make sure that the write went through before we exit this call. [...] >> + list_del(&resp->list); >> + spin_unlock_irqrestore(&drv->drv_lock, flags); >> + free_response(resp); > >But all this function does is free the structure? Will it do more later? > Hopefully, I would like to use a pre-allocateed pool instead of alloc and free. > + for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) { >> + addr = read_tcs_reg(drv, RSC_DRV_CMD_ADDR, m, j); >> + for (k = 0; k < msg->num_payload; k++) { >> + if (addr == msg->payload[k].addr) >> + return -EBUSY; >> + } >> + } >> + } > >There isn't any way to do this in software only? Hopefully this isn't >costly to read the TCS to see if something matches. > It is, but not too expensive. The alternatives involves more locking.. Thanks, Lina