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[108.223.40.66]) by smtp.gmail.com with ESMTPSA id w129sm5028622pfd.155.2018.03.09.14.06.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 14:06:10 -0800 (PST) Date: Fri, 9 Mar 2018 14:06:10 -0800 From: Guenter Roeck To: Eddie James Cc: linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, joel@jms.id.au, wim@linux-watchdog.org, Milton Miller Subject: Re: [PATCH 2/2] watchdog: aspeed: Allow configuring for alternate boot Message-ID: <20180309220610.GB32606@roeck-us.net> References: <1520632700-25800-1-git-send-email-eajames@linux.vnet.ibm.com> <1520632700-25800-3-git-send-email-eajames@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1520632700-25800-3-git-send-email-eajames@linux.vnet.ibm.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 09, 2018 at 03:58:20PM -0600, Eddie James wrote: > From: Milton Miller > > Allow the device tree to specify a watchdog to fallover to > the alternate boot source. > > The aspeeed watchdog can set a latch directing flash chip select 0 to > chip select 1, allowing boot from an alternate media if the watchdog > is not reset in time. On the ast2400 bank 1 also goes to flash bank 1, > while on the ast2500 the chip selects are swapped. > > Signed-off-by: Milton Miller > Signed-off-by: Eddie James This is already documented in the bindings document, so the property should be ok. Reviewed-by: Guenter Roeck > --- > drivers/watchdog/aspeed_wdt.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c > index d1987d6..f41d246 100644 > --- a/drivers/watchdog/aspeed_wdt.c > +++ b/drivers/watchdog/aspeed_wdt.c > @@ -46,6 +46,7 @@ struct aspeed_wdt_config { > #define WDT_RELOAD_VALUE 0x04 > #define WDT_RESTART 0x08 > #define WDT_CTRL 0x0C > +#define WDT_CTRL_BOOT_SECONDARY BIT(7) > #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) > #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) > #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) > @@ -245,6 +246,8 @@ static int aspeed_wdt_probe(struct platform_device *pdev) > } > if (of_property_read_bool(np, "aspeed,external-signal")) > wdt->ctrl |= WDT_CTRL_WDT_EXT; > + if (of_property_read_bool(np, "aspeed,alt-boot")) > + wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY; > > if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { > /* > -- > 1.8.3.1 >