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[209.132.180.67]) by mx.google.com with ESMTP id t11-v6si1638775plr.411.2018.03.09.15.02.03; Fri, 09 Mar 2018 15:02:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932557AbeCIXBH (ORCPT + 99 others); Fri, 9 Mar 2018 18:01:07 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:42564 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932186AbeCIXBG (ORCPT ); Fri, 9 Mar 2018 18:01:06 -0500 Received: from p4fea5f09.dip0.t-ipconnect.de ([79.234.95.9] helo=nanos.glx-home) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1euR0T-0000gS-2C; Sat, 10 Mar 2018 00:00:57 +0100 Date: Sat, 10 Mar 2018 00:00:56 +0100 (CET) From: Thomas Gleixner To: Palmer Dabbelt cc: linux@armlinux.org.uk, catalin.marinas@arm.com, Will Deacon , jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openrisc@lists.librecores.org, linux-riscv@lists.infradead.org, linux@arm.linux.org.uk Subject: Re: Make set_handle_irq and handle_arch_irq generic, v3 In-Reply-To: Message-ID: References: User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 9 Mar 2018, Palmer Dabbelt wrote: > On Fri, 09 Mar 2018 02:20:12 PST (-0800), tglx@linutronix.de wrote: > > This looks sensible. We have two options for getting this merged: > > > > 1) I'll take the whole lot through tip/irq/core > > > > 2) I'll apply patch 1/N to a special branch in tip. That branch will > > contain > > only this commit on top of 4.16-rc4 and can be pulled by the relevant > > architecture maintainers, so they can apply their architecture specific > > patches. > > Option 1 seems like the lowest overhead, as that way we don't need to sequence > the patches between multiple trees. If all the other arch maintianers are OK > with it then that works for me. Ok, I wait for someone to yell NO until tuesday. If that doesn't happen I pick it up. > The 0-day robot found a new build warning on openrisc. I was plannning > on submitting a v4 with this fix in it > > diff --git a/arch/openrisc/include/asm/irq.h > b/arch/openrisc/include/asm/irq.h > index d9eee0a2b7b4..eb612b1865d2 100644 > --- a/arch/openrisc/include/asm/irq.h > +++ b/arch/openrisc/include/asm/irq.h > @@ -24,6 +24,4 @@ > #define NO_IRQ (-1) > -extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); > - > #endif /* __ASM_OPENRISC_IRQ_H__ */ > > I can submit a v4, or you can just grab it from Just reply on the v3 openrisc patch with a v4 and I grab it from there. Thanks, tglx