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Date:   Sat, 10 Mar 2018 12:20:19 +0000
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From:   Marc Zyngier <marc.zyngier@arm.com>
To:     Christoffer Dall <cdall@kernel.org>
Cc:     Shunyong Yang <shunyong.yang@hxt-semitech.com>,
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        linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu,
        linux-kernel@vger.kernel.org,
        Joey Zheng <yu.zheng@hxt-semitech.com>
Subject: Re: [RFC PATCH] KVM: arm/arm64: vgic: change condition for level interrupt resampling
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On Fri, 09 Mar 2018 21:36:12 +0000,
Christoffer Dall wrote:
> 
> On Thu, Mar 08, 2018 at 05:28:44PM +0000, Marc Zyngier wrote:
> > I'd be more confident if we did forbid P+A for such interrupts
> > altogether, as they really feel like another kind of HW interrupt.
> 
> How about a slightly bigger hammer:  Can we avoid doing P+A for level
> interrupts completely?  I don't think that really makes much sense, and
> I think we simply everything if we just come back out and resample the
> line.  For an edge, something like a network card, there's a potential
> performance win to appending a new pending state, but I doubt that this
> is the case for level interrupts.

I started implementing the same thing yesterday. Somehow, it feels
slightly better to have the same flow for all level interrupts,
including the timer, and we only use the MI on EOI as a way to trigger
the next state of injection. Still testing, but looking good so far.

I'm still puzzled that we have this level-but-not-quite behaviour for
VFIO interrupts. At some point, it is going to bite us badly.

	M.

-- 
Jazz is not dead, it just smell funny.