Received: by 10.213.65.16 with SMTP id m16csp202586imf; Mon, 12 Mar 2018 00:05:11 -0700 (PDT) X-Google-Smtp-Source: AG47ELthdAoQrQGvSzbPl229/UhUAfDwDeYAsUG0z6gzBpdKC+R1opi9S6fpLEeE1SJwmUlxN3XB X-Received: by 10.99.120.201 with SMTP id t192mr5775795pgc.39.1520838311089; Mon, 12 Mar 2018 00:05:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520838311; cv=none; d=google.com; s=arc-20160816; b=eWuO4RiwHOf5Kbv3XD/2Tep4WstpuzNKb+fidsXw2JUL6mX9MtYaG6bcajqNcDJobQ mta2Xs/W19PbADvAg1nrFwcgPUmQttYsjpCOZ9L6PvFNxcgrsp0NXL8B9ekH7sW2xD+M vrlCtCSlBI2Z69K6nLfIx7lg1hPc7ih8uy1zt1srO0O0y6bGi8SUELLc6YT6IbJNepKN 5jLwgdq1u1VdvUnIMuqwLaL9gzj+gFalGsDhhYoNGrMTm8dXlM4K7P/JuKgYwV847EcP BSHn0NxbtCaH6KjME4iKhZd1+PmMUAPPEqNWadHVUX6IhslCQXUs3KgJlGfLS6dRK2ci dsUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=52f1EXcVjsrmFJfALEaTn/j/1iIa6V39UQDPZfa1hNs=; b=lK9LF0/C5X0tAolOt4z3fhHpaA72iN1x5xGj61BxASnXOqKlixcFamoPhgmvkg5oYK 0RLx+KfCgpC5hVlDpXihP5PiILDThNJG8Z/hDgMgzgBDBB+U6h9x7yL8RCe64rDE9JGD iIHxtA2YIlVJOjHCTCugA48a37ulJm2IIMNXw47lZ7YdHyk2SU85TOTf58wWTn0KeV6u 7v4sY0XThVxh3xGf8591mXF0/GtZtH2I+SOUNQ7K38OEUTOVU7di5xDIXjR2ZhHprbZK a9s7GQEsIb/izGqJakos/4SVEEIek9sIJRyY32KqwUqjU23U4tHqGDz8p//frqLvXGNs wRrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u19si4541458pgv.755.2018.03.12.00.04.56; Mon, 12 Mar 2018 00:05:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932582AbeCLHD6 (ORCPT + 99 others); Mon, 12 Mar 2018 03:03:58 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:53066 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751878AbeCLHDz (ORCPT ); Mon, 12 Mar 2018 03:03:55 -0400 X-UUID: 5a42b65423b84cfea677db6b9c720863-20180312 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 328451514; Mon, 12 Mar 2018 15:03:51 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 12 Mar 2018 15:03:44 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 12 Mar 2018 15:03:44 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Mike Turquette , Rob Herring CC: James Liao , Fan Chen , , , , , , , Weiyi Lu Subject: [PATCH v2 0/5] update Mediatek MT2712 clock and scpsys support Date: Mon, 12 Mar 2018 15:03:37 +0800 Message-ID: <20180312070342.4335-2-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20180312070342.4335-1-weiyi.lu@mediatek.com> References: <20180312070342.4335-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2) and clock control (PATCH 3-5). Basically, all changes are for the ECO design change of MT2712. changes since v1: - Avoid renumbering clocks. Append new clocks at the bottom of each own subsystem. Weiyi Lu (5): dt-bindings: soc: update MT2712 power dt-bindings soc: mediatek: update power domain data of MT2712 dt-bindings: clock: add clocks for MT2712 arm64: dts: add clock device nodes of MT2712 clk: mediatek: update clock driver of MT2712 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 +++++++++++++ drivers/clk/mediatek/clk-mt2712.c | 69 ++++++++++++++++++++++++------- drivers/soc/mediatek/mtk-scpsys.c | 42 ++++++++++++++++++- include/dt-bindings/clock/mt2712-clk.h | 12 +++++- include/dt-bindings/power/mt2712-power.h | 3 ++ 5 files changed, 136 insertions(+), 18 deletions(-) -- 2.12.5