Received: by 10.213.65.16 with SMTP id m16csp203305imf; Mon, 12 Mar 2018 00:07:14 -0700 (PDT) X-Google-Smtp-Source: AG47ELv2ns4dCxb/XhG8xdgAHVwyVPL5gLGdnRLLVbTJPZlbwbv+WadXz2Gb8CbdGlSLJ9G1JWXr X-Received: by 2002:a17:902:b2c6:: with SMTP id x6-v6mr4885444plw.298.1520838434581; Mon, 12 Mar 2018 00:07:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520838434; cv=none; d=google.com; s=arc-20160816; b=AzLzQASiVJlE1rpGZ2HJ9YKAyj0CQeNDlX9r+f8CJdH+wvvWbW0s/TRjw0aHZFLBAA N3x64xEvsPePlYBdAic45ibHxwtnLCgV/a91kSiPaChEv/Tu+34VXDXFxZ5n8go1+u3c phHIQvLduzMrb093FOJk2ZQRrMhp8d4ksm3K7UQ9su7AS40/F5tWLdWp0wA5k1xhNJQu uvmHNJnxsln8hzeAYU977aBcleqcJaWf8BxlYcOcTz40tBwJsDeRf6KVNiap5HO0ZQzz PEKFv6cSiH+/0QNpuEvw+wH3rNqVLO3GCWh+qmlXUAglDm3z+l7Sc6MpUzsLZCQKIrvH 7WVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=hCh2z9nJlso04pdI+LfCsvMLaEHndr6irqIVC97sFOw=; b=chrqCdL0QCcx2o/ZteuACrhutd2bmTMXOd+wW487O5iXYeoz0hiayLAfqV2nanj/YM xzGueG3nIxkhtlwVBW4/3v5W5PcJEv/LQaaYtsXYoRsziMWb+Af4lSNNFMH6D6ZsBQpX 4v6w53SDcDhINvx2D5a1+BIstWh7BdYsnlDQsonnMC3nH9R01me/uBm52JezfXo8pB3w khliaLNA97stK1HfTvlnxPyE49txrXa4Qo75XEb6yLCG1fYJ9VOqK78g+Q+7cr1YwBfL VWObxtwV47ieRORCokjmEvkeXGTdtvY8ipWnNSRyVvxdxRQwmEhkdHRnfpyP5OU68kDN Ql3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k17si5050606pff.157.2018.03.12.00.07.00; Mon, 12 Mar 2018 00:07:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752268AbeCLHFc (ORCPT + 99 others); Mon, 12 Mar 2018 03:05:32 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47181 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751903AbeCLHDu (ORCPT ); Mon, 12 Mar 2018 03:03:50 -0400 X-UUID: 7dc9f3ab743941efb0fd4f947a5c18af-20180312 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 246709532; Mon, 12 Mar 2018 15:03:45 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 12 Mar 2018 15:03:44 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 12 Mar 2018 15:03:44 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Mike Turquette , Rob Herring CC: James Liao , Fan Chen , , , , , , , Weiyi Lu Subject: [PATCH v2 3/5] dt-bindings: clock: add clocks for MT2712 Date: Mon, 12 Mar 2018 15:03:40 +0800 Message-ID: <20180312070342.4335-5-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20180312070342.4335-1-weiyi.lu@mediatek.com> References: <20180312070342.4335-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org add new clocks according to ECO design change Signed-off-by: Weiyi Lu --- include/dt-bindings/clock/mt2712-clk.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h index 48a8e797a617..76265836a1e1 100644 --- a/include/dt-bindings/clock/mt2712-clk.h +++ b/include/dt-bindings/clock/mt2712-clk.h @@ -222,7 +222,13 @@ #define CLK_TOP_APLL_DIV_PDN5 183 #define CLK_TOP_APLL_DIV_PDN6 184 #define CLK_TOP_APLL_DIV_PDN7 185 -#define CLK_TOP_NR_CLK 186 +#define CLK_TOP_APLL1_D3 186 +#define CLK_TOP_APLL1_REF_SEL 187 +#define CLK_TOP_APLL2_REF_SEL 188 +#define CLK_TOP_NFI2X_EN 189 +#define CLK_TOP_NFIECC_EN 190 +#define CLK_TOP_NFI1X_CK_EN 191 +#define CLK_TOP_NR_CLK 192 /* INFRACFG */ @@ -281,7 +287,9 @@ #define CLK_PERI_MSDC30_3_EN 41 #define CLK_PERI_MSDC50_0_HCLK_EN 42 #define CLK_PERI_MSDC50_3_HCLK_EN 43 -#define CLK_PERI_NR_CLK 44 +#define CLK_PERI_MSDC30_0_QTR_EN 44 +#define CLK_PERI_MSDC30_3_QTR_EN 45 +#define CLK_PERI_NR_CLK 46 /* MCUCFG */ -- 2.12.5