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[209.132.180.67]) by mx.google.com with ESMTP id x11-v6si2133286pll.681.2018.03.12.09.46.42; Mon, 12 Mar 2018 09:46:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@chromium.org header.s=google header.b=nAomoZPU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932526AbeCLQph (ORCPT + 99 others); Mon, 12 Mar 2018 12:45:37 -0400 Received: from mail-oi0-f68.google.com ([209.85.218.68]:33495 "EHLO mail-oi0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751787AbeCLQpe (ORCPT ); Mon, 12 Mar 2018 12:45:34 -0400 Received: by mail-oi0-f68.google.com with SMTP id e9so12877897oii.0 for ; Mon, 12 Mar 2018 09:45:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=ArsIhtyHbK+dqnHM11WArY7FFeC3t/6NBEQr/vqt2Yk=; b=nAomoZPUHsg4x9FeHq2uBnz/cabMgNq4Q/04QXSabaaXX6JfUGqr9XjZW1TKG/VS/O ZKn/aYA4SWOAwis0pGeygH8LL+Z55Wov+2qNPUYmA855bkVrTyeAE8iC8K1lA9ib62BD InX6to7DL99Q3d789LNfg8ep3QEwLEHdGe4C8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ArsIhtyHbK+dqnHM11WArY7FFeC3t/6NBEQr/vqt2Yk=; b=gPH/Uf5wNTedDv0job7Mf9QXkpvnWBY7dprGJsG88ScAe4OAhH9LJDMSVbtPMk9qI3 1I+A3hPa2Zj1TaFsgGbDtptokt8wwzHZvMkY9AXHk9V+sbvVrepKl6Z+env5X/Mw5WkO qTeutXng3itBgizrdoZ6KFa3cSV5wLC1IP+mhdhe6z/8SSEB3nKZRs/y+W16BL8pEi6z vITT/YuxyGcmdIihYMIKLEbrbgHp7zL5PtwS1Z98ODQUsyilvZJTqZ1/1VMqnXdnI/IR rCbNElXmI9uSeysxCY/nZXonJfyXwSrguWZI7SSTSzCGwSM61r1JKaR+FS0+aJy28Eu0 6hag== X-Gm-Message-State: AElRT7GO5lujKbknId49/sVhlPRh4NGGKWXXnbMm10F2rCYrPRK1bXgu Koq3Ny9T/SVp7tqiqukNy0mkIw== X-Received: by 10.202.225.67 with SMTP id y64mr5600239oig.122.1520873134156; Mon, 12 Mar 2018 09:45:34 -0700 (PDT) Received: from djkurtz2.bld.corp.google.com ([2620:15c:183:0:1cfd:61a5:7215:5f9c]) by smtp.gmail.com with ESMTPSA id w199sm3600797oiw.29.2018.03.12.09.45.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Mar 2018 09:45:33 -0700 (PDT) From: Daniel Kurtz Cc: adurbin@chromium.org, Daniel Kurtz , Linus Walleij , linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] pinctrl/amd: poll InterruptEnable bits in enable_irq Date: Mon, 12 Mar 2018 10:45:30 -0600 Message-Id: <20180312164530.215524-1-djkurtz@chromium.org> X-Mailer: git-send-email 2.16.2.660.g709887971b-goog To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In certain cases interrupt enablement will be delayed relative to when the InterruptEnable bits are written. One example of this is when a GPIO's "debounce" logice is first enabled. After enabling debounce, there is a 900 us "warm up" period during which InterruptEnable[0] (bit 11) will read as 0 despite being written 1. During this time InterruptSts will not be updated, nor will interrupts be delivered, even if the GPIO's interrupt configuration has been written to the register. To work around this delay, poll the InterruptEnable bits after setting them to ensure interrupts have truly been enabled in hardware before returning from the irq_enable handler. Signed-off-by: Daniel Kurtz --- drivers/pinctrl/pinctrl-amd.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index dae184c4b962..af8ef485fbe7 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -348,12 +348,21 @@ static void amd_gpio_irq_enable(struct irq_data *d) unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF); raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg |= BIT(INTERRUPT_ENABLE_OFF); pin_reg |= BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + /* + * When debounce logic is enabled it takes ~900 us before interrupts + * can be enabled. During this "debounce warm up" period the + * "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it + * reads back as 1, signaling that interrupts are now enabled. + */ + while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) + continue; raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } -- 2.16.2.660.g709887971b-goog