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[209.132.180.67]) by mx.google.com with ESMTP id s12si6236305pgq.491.2018.03.13.01.53.36; Tue, 13 Mar 2018 01:53:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932312AbeCMIsT (ORCPT + 99 others); Tue, 13 Mar 2018 04:48:19 -0400 Received: from exmail.andestech.com ([59.124.169.137]:62208 "EHLO ATCSQR.andestech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752038AbeCMIsR (ORCPT ); Tue, 13 Mar 2018 04:48:17 -0400 X-Greylist: delayed 679 seconds by postgrey-1.27 at vger.kernel.org; Tue, 13 Mar 2018 04:48:17 EDT Received: from ATCSQR.andestech.com (localhost [127.0.0.2] (may be forged)) by ATCSQR.andestech.com with ESMTP id w2D8XTHY025114 for ; Tue, 13 Mar 2018 16:33:29 +0800 (GMT-8) (envelope-from zong@andestech.com) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id w2D8Wt9W024930; Tue, 13 Mar 2018 16:32:55 +0800 (GMT-8) (envelope-from zong@andestech.com) Received: from atcsqa06.andestech.com (10.0.1.85) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Tue, 13 Mar 2018 16:36:22 +0800 From: Zong Li To: , , , , , CC: Subject: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit Date: Tue, 13 Mar 2018 16:35:05 +0800 Message-ID: X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.0.1.85] X-DNSRBL: X-MAIL: ATCSQR.andestech.com w2D8Wt9W024930 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These patches resolve the some issues of loadable module. - symbol out of ranges - unknown relocation types The reference of external variable and function symbols cannot exceed 32-bit offset ranges in kernel module. The module only can work on the 32-bit OS or the 64-bit OS with sv32 virtual addressing. These patches will generate the .got, .got.plt and .plt sections during loading module, let it can refer to the symbol which locate more than 32-bit offset. These sections depend on the relocation types: - R_RISCV_GOT_HI20 - R_RISCV_CALL_PLT These patches also support more relocation types - R_RISCV_CALL - R_RISCV_HI20 - R_RISCV_LO12_I - R_RISCV_LO12_S - R_RISCV_RVC_BRANCH - R_RISCV_RVC_JUMP - R_RISCV_ALIGN - R_RISCV_ADD32 - R_RISCV_SUB32 Zong Li (11): RISC-V: Add sections of PLT and GOT for kernel module RISC-V: Add section of GOT.PLT for kernel module RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module RISC-V: Support CALL relocation type in kernel module RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewq RISC-V: Support ALIGN relocation type in kernel module RISC-V: Support ADD32 relocation type in kernel module RISC-V: Support SUB32 relocation type in kernel module RISC-V: Enable module support in defconfig RISC-V: Add definition of relocation types arch/riscv/Kconfig | 5 ++ arch/riscv/Makefile | 3 + arch/riscv/configs/defconfig | 2 + arch/riscv/include/asm/module.h | 112 +++++++++++++++++++++++ arch/riscv/include/uapi/asm/elf.h | 24 +++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/module-sections.c | 156 ++++++++++++++++++++++++++++++++ arch/riscv/kernel/module.c | 175 ++++++++++++++++++++++++++++++++++-- arch/riscv/kernel/module.lds | 8 ++ 9 files changed, 480 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/include/asm/module.h create mode 100644 arch/riscv/kernel/module-sections.c create mode 100644 arch/riscv/kernel/module.lds -- 2.16.1