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[209.132.180.67]) by mx.google.com with ESMTP id n9-v6si128787pll.695.2018.03.13.06.51.50; Tue, 13 Mar 2018 06:52:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752963AbeCMNu6 (ORCPT + 99 others); Tue, 13 Mar 2018 09:50:58 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:53655 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752849AbeCMNu4 (ORCPT ); Tue, 13 Mar 2018 09:50:56 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w2DDmdYY030616; Tue, 13 Mar 2018 14:50:37 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2gpc5s96y6-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 13 Mar 2018 14:50:37 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0C7B838; Tue, 13 Mar 2018 13:50:37 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8B62955D3; Tue, 13 Mar 2018 13:50:36 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 13 Mar 2018 14:50:36 +0100 Received: from localhost (10.201.23.68) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 13 Mar 2018 14:50:36 +0100 From: yannick fertre To: Vikas Manocha , Tom Rini , Benjamin Gaignard , Yannick Fertre , Philippe Cornu , "Patrice Chotard" , Patrick DELAUNAY , Christophe KERELLO , Archit Taneja , Andrzej Hajda , "Laurent Pinchart" , David Airlie , Brian Norris , Bhumika Goyal , Gustavo Padovan , "Maarten Lankhorst" , Sean Paul , Albert Aribaud , "Simon Glass" , Anatolij Gustschin , Thierry Reding CC: , , Subject: [PATCH v3 09/10] arm: dts: stm32: add display for STM32F769 disco board Date: Tue, 13 Mar 2018 14:50:12 +0100 Message-ID: <1520949014-21468-14-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520949014-21468-1-git-send-email-yannick.fertre@st.com> References: <1520949014-21468-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.68] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-03-13_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the display controller, mipi dsi bridge & panel. Set panel display timings. Signed-off-by: yannick fertre --- arch/arm/dts/stm32f769-disco.dts | 71 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 59c9d31..82985b9 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "stm32f746.dtsi" +#include #include / { @@ -264,3 +265,73 @@ bus-width = <4>; max-frequency = <25000000>; }; + +<dc { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel-dsi@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + display-timings { + timing@0 { + clock-frequency = <32729000>; + hactive = <480>; + hfront-porch = <120>; + hback-porch = <63>; + hsync-len = <120>; + vactive = <800>; + vfront-porch = <12>; + vback-porch = <12>; + vsync-len = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; +}; -- 1.9.1