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[209.132.180.67]) by mx.google.com with ESMTP id q4-v6si326643plr.365.2018.03.13.09.36.53; Tue, 13 Mar 2018 09:37:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WXGWIDGH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933691AbeCMQfg (ORCPT + 99 others); Tue, 13 Mar 2018 12:35:36 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:46604 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933069AbeCMQfe (ORCPT ); Tue, 13 Mar 2018 12:35:34 -0400 Received: by mail-qk0-f193.google.com with SMTP id o184so220598qkd.13; Tue, 13 Mar 2018 09:35:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=mcrOHgebNDKh9UMidNc4UPOVhmZtyhPntLezCJPhaNQ=; b=WXGWIDGHszb+fVO9ye6b+7uElAX/mxe6IMLFkWWmb2aNF7MrPoMrqdl3vG1DpuqYSx rpeO+Kmg+2V0TepTqOKWylg7AgxUFcl4V9bPGptuti/5hF2dsfWG3tWzHNQ0exb1xfTn I4Otl+EedSbsYWCZDiCftnCaF0O+j6EPKjPZ1CSDL3NKrGe8q11msce9Y9Sdai5RgiYT jlPlqE1Q3O1WIN2AgNwvGWGuMG5z40dsGjzYVcLITbjC2aiwasJ/pBPpi2y6favQHGUm s8jBsRwUFruy2we9btQjlEcOOLCVD/r2OaMPurqXTOQ6cDqLF0Qx76C8zXRUrARRaZ3r ujOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=mcrOHgebNDKh9UMidNc4UPOVhmZtyhPntLezCJPhaNQ=; b=IAACmpygWYSNPRrxqNKg/CipyCkRNvextkKVfWBZz3Gd23fqiv69/jKum87urKV8hy 9uIvHIuTWjT0Op1OLncTcZDXnw4gSe7J1sNpf6i3aKX3yOqnOsNLOktCWcv9t7lWhaQx rMFYaLHmObCR/upn4ajzjED1lbFIo/fJLY8HPEJPoJPUxdK4Yb26qiqZIP+UKIkHWbAJ dtaB6/1RL5wX9vWZc3jxSSYHsx/VzAR59q2Qg0zv8ruWy9kGn3zaHRKmZIDeynHx+pcy OCu6ckVq7vQAN4imky9bfURCq/uLiz+pN2ytjhKs/qRJPyjuwQihFbwAC1z9hQ05Ufxs mWYA== X-Gm-Message-State: AElRT7FKESVvxxFV35HMFBfgAJYXRl4HTRyghFv26Q3gbsRI9zz17CVg n+RFEvE7g18W4L+1HPuNpZTROxddY4bIK/meURZVuVZ3 X-Received: by 10.55.245.14 with SMTP id l14mr1852238qkk.301.1520958933193; Tue, 13 Mar 2018 09:35:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.195.80 with HTTP; Tue, 13 Mar 2018 09:35:32 -0700 (PDT) In-Reply-To: <1520879456-14777-1-git-send-email-phil.edworthy@renesas.com> References: <1520879456-14777-1-git-send-email-phil.edworthy@renesas.com> From: Andy Shevchenko Date: Tue, 13 Mar 2018 18:35:32 +0200 Message-ID: Subject: Re: [PATCH v2] gpio: dwapb: Add support for a bus clock To: Phil Edworthy Cc: Hoan Tran , Linus Walleij , Michel Pollet , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 12, 2018 at 8:30 PM, Phil Edworthy wrote: > Enable an optional bus clock provided by DT. FWIW, Reviewed-by: Andy Shevchenko (Assuming it has been tested on clock-less cases) > Signed-off-by: Phil Edworthy > --- > v2: > - Fix include order. > - Use a clock name. > - Check errors from clk_prepare_enable() > - Add calls to enable/disable the clock in PM > --- > drivers/gpio/gpio-dwapb.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c > index b0704a8..226977f 100644 > --- a/drivers/gpio/gpio-dwapb.c > +++ b/drivers/gpio/gpio-dwapb.c > @@ -8,8 +8,9 @@ > * All enquiries to support@picochip.com > */ > #include > -#include > +#include > #include > +#include > #include > #include > #include > @@ -98,6 +99,7 @@ struct dwapb_gpio { > struct irq_domain *domain; > unsigned int flags; > struct reset_control *rst; > + struct clk *clk; > }; > > static inline u32 gpio_reg_v2_convert(unsigned int offset) > @@ -670,6 +672,16 @@ static int dwapb_gpio_probe(struct platform_device *pdev) > if (IS_ERR(gpio->regs)) > return PTR_ERR(gpio->regs); > > + /* Optional bus clock */ > + gpio->clk = devm_clk_get(&pdev->dev, "bus"); > + if (!IS_ERR(gpio->clk)) { > + err = clk_prepare_enable(gpio->clk); > + if (err) { > + dev_info(&pdev->dev, "Cannot enable clock\n"); > + return err; > + } > + } > + > gpio->flags = 0; > if (dev->of_node) { > const struct of_device_id *of_devid; > @@ -712,6 +724,7 @@ static int dwapb_gpio_remove(struct platform_device *pdev) > dwapb_gpio_unregister(gpio); > dwapb_irq_teardown(gpio); > reset_control_assert(gpio->rst); > + clk_disable_unprepare(gpio->clk); > > return 0; > } > @@ -757,6 +770,8 @@ static int dwapb_gpio_suspend(struct device *dev) > } > spin_unlock_irqrestore(&gc->bgpio_lock, flags); > > + clk_disable_unprepare(gpio->clk); > + > return 0; > } > > @@ -768,6 +783,9 @@ static int dwapb_gpio_resume(struct device *dev) > unsigned long flags; > int i; > > + if (!IS_ERR(gpio->clk)) > + clk_prepare_enable(gpio->clk); > + > spin_lock_irqsave(&gc->bgpio_lock, flags); > for (i = 0; i < gpio->nr_ports; i++) { > unsigned int offset; > -- > 2.7.4 > -- With Best Regards, Andy Shevchenko