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[209.132.180.67]) by mx.google.com with ESMTP id g2-v6si294453plo.567.2018.03.13.09.37.00; Tue, 13 Mar 2018 09:37:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933633AbeCMQe6 (ORCPT + 99 others); Tue, 13 Mar 2018 12:34:58 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:19026 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933458AbeCMQez (ORCPT ); Tue, 13 Mar 2018 12:34:55 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w2DGYHg0010426; Tue, 13 Mar 2018 17:34:28 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2gpc5s9yqm-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 13 Mar 2018 17:34:28 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D42B931; Tue, 13 Mar 2018 16:34:26 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag4node2.st.com [10.75.127.11]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DFBE1A61F; Tue, 13 Mar 2018 16:34:25 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG4NODE2.st.com (10.75.127.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 13 Mar 2018 17:34:25 +0100 From: To: Philipp Zabel , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , CC: , , , , Loic PALLARDY , benjamin GAIGNARD , Michael Turquette , , Gabriel Fernandez Subject: [PATCH 0/2] Introduce STM32MP1 Reset driver Date: Tue, 13 Mar 2018 17:34:17 +0100 Message-ID: <1520958859-27911-1-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG4NODE2.st.com (10.75.127.11) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-03-13_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Gabriel Fernandez This patch-set enables the reset of STM32MP1. It uses the reset simple driver by introducing the clear register offset parameter. STM32MP1 reset IP has a register to assert by writing '1' and another register to de-assert by writing '1'. The offset between this two registers is '0x4'. The patch 'dt-bindings: reset: add STM32MP1 resets' could be squashed with the patch: 'dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings' commit 3830681d354f Gabriel Fernandez (2): dt-bindings: reset: add STM32MP1 resets reset: simple: Enable stm32mp1 reset driver drivers/reset/reset-simple.c | 27 +++++-- drivers/reset/reset-simple.h | 1 + include/dt-bindings/reset/stm32mp1-resets.h | 108 ++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h -- 1.9.1