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From:   Heiko Stuebner <heiko@sntech.de>
To:     Derek Basehore <dbasehore@chromium.org>
Cc:     linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
        sboyd@kernel.org, mturquette@baylibre.com
Subject: Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate
Date:   Wed, 14 Mar 2018 00:38:40 +0100
Message-ID: <13704601.M15qmmjcHi@phil>
In-Reply-To: <20180313203719.75639-1-dbasehore@chromium.org>
References: <20180313203719.75639-1-dbasehore@chromium.org>
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Am Dienstag, 13. M?rz 2018, 21:37:19 CET schrieb Derek Basehore:
> We need this rate to generate 100, 200, and 228.57MHz from the same
> PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
> and external display.
> 
> Signed-off-by: Derek Basehore <dbasehore@chromium.org>

applied for 4.17

Thanks
Heiko