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[209.132.180.67]) by mx.google.com with ESMTP id s12si1641440pgq.491.2018.03.14.03.37.31; Wed, 14 Mar 2018 03:37:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WhVD9h2x; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751740AbeCNKf7 (ORCPT + 99 others); Wed, 14 Mar 2018 06:35:59 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:33762 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751372AbeCNKf4 (ORCPT ); Wed, 14 Mar 2018 06:35:56 -0400 Received: by mail-qk0-f193.google.com with SMTP id f25so2890214qkm.0; Wed, 14 Mar 2018 03:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=HKe+lYRpzLhjdsdCdjng2PrGr2F3ca+m0AGeYEuJowQ=; b=WhVD9h2xc9DZbxRwbyUYw/Kv21Fg/duWmd/Z9c2PUqy/QbZqMdo52b/rjDhcV0IrhK EQxRHvAtPWugfsFV7N0uMGGIE71uC8HVmzb4JH/E1ZB/CUpVZ5ipXO8odE2TVyn0O4oW fM6V0hfGKkkbaX1fK8O6HEqbS9w5thjNYixLR91qWiih/GeoslS6s8/qAkTDAeHgQq6T zBcylxQPesYIVOvNDMkrOIpxWuN7ca2CXcRKXqN/WpnPBnD/90cu/c+7Ohk6D2h0SYkc cET3CHN5xCNHhvlmwNxWjAmYKSMibVnTFClpsIhAWeXW3TlYiPmPrqX4zusBknpEUIRl CFkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=HKe+lYRpzLhjdsdCdjng2PrGr2F3ca+m0AGeYEuJowQ=; b=QIUAHCike2qfMEAJ+/YWUTbhOX0iBgJSdV0i5OiwTji+KN5AewGGS2fbmtdUF/C1gN BPRCyvFKquRf4t+sJ6HG7KzXQvuG4KXGo9ZzUdYKvqUtH3bTUyBme3uxzexy4PLrwLUZ ngj+cby1WHxLXfiopEnpYbqz3di+6eib3GCfKNrBY4QGc5zjtVVogXPW/pKrDk9YRlNs w2Hoj23AW07Yl/OX25aSlyn/wq4GDBS6N2I05rHjwA0zcxUIut3FiV4isBOyKXHhK4VV ZmadiCAwZij/leGmk0ARjNSvhZZ5tx0AGvfTo7Z96hfEDGshrQ9j0Qj6cmgnydHoI9uY GBdA== X-Gm-Message-State: AElRT7Emcvw954sDp5VdJeXfz3tGR3kb2uNvouQqdd1eGj3B8SUGTVwI X3EILCsgjnyy5K4IOrfmfFb8AHJ0H63zX+4U6VU= X-Received: by 10.55.126.69 with SMTP id z66mr5735724qkc.218.1521023755701; Wed, 14 Mar 2018 03:35:55 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.195.80 with HTTP; Wed, 14 Mar 2018 03:35:55 -0700 (PDT) In-Reply-To: <20180314003655.12141-2-djkurtz@chromium.org> References: <20180314003655.12141-1-djkurtz@chromium.org> <20180314003655.12141-2-djkurtz@chromium.org> From: Andy Shevchenko Date: Wed, 14 Mar 2018 12:35:55 +0200 Message-ID: Subject: Re: [PATCH 1/3] serial: 8250_early: Add earlycon support for AMD Carrizo / Stoneyridge To: Daniel Kurtz Cc: Aaron Durbin , Greg Kroah-Hartman , Jiri Slaby , Marc Gonzalez , Douglas Anderson , Matt Redfearn , Jeffy Chen , "open list:SERIAL DRIVERS" , open list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 14, 2018 at 2:36 AM, Daniel Kurtz wrote: > AMD Carrizo / Stoneyridge use a DesignWare 8250 UART that uses a 48 MHz > input clock. > > Allow these platforms to set up this clock by specifying a kernel command > line like: > earlycon=amdcz,mmio32,0xfedc6000,115200 > Thanks, this is what I meant. Reviewed-by: Andy Shevchenko Suggested-by: ? > Signed-off-by: Daniel Kurtz > --- > drivers/tty/serial/8250/8250_early.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c > index ae6a256524d8..c6bf971a6038 100644 > --- a/drivers/tty/serial/8250/8250_early.c > +++ b/drivers/tty/serial/8250/8250_early.c > @@ -195,3 +195,18 @@ static int __init early_au_setup(struct earlycon_device *dev, const char *opt) > OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup); > > #endif > + > +#ifdef CONFIG_SERIAL_8250_DW > +static int __init early_amdcz_setup(struct earlycon_device *dev, > + const char *opt) > +{ > + struct uart_port *port = &dev->port; > + > + port->uartclk = 48000000; > + > + return early_serial8250_setup(dev, opt); > +} > + > +EARLYCON_DECLARE(amdcz, early_amdcz_setup); > + > +#endif > -- > 2.16.2.804.g6dcf76e118-goog > -- With Best Regards, Andy Shevchenko