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[209.132.180.67]) by mx.google.com with ESMTP id j9si1708528pgc.72.2018.03.14.03.56.23; Wed, 14 Mar 2018 03:56:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=LBjOekwX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751649AbeCNKyJ (ORCPT + 99 others); Wed, 14 Mar 2018 06:54:09 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:43032 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751440AbeCNKyF (ORCPT ); Wed, 14 Mar 2018 06:54:05 -0400 Received: by mail-lf0-f65.google.com with SMTP id q69-v6so4055501lfi.10; Wed, 14 Mar 2018 03:54:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=NeQpk86S0vBOYYtLpIAqK8kTWLQJ7iK7jzELiikKnw4=; b=LBjOekwXjduoE/XJirvtdgDpUGKHE6QjToC6ORn7ZQFJql6hiiJDd7/AI47DUnZiOr dSjQJ082SZb9t9D4zamjyWO994eJ1yG0UF3B3awDEJcq15NeCaIQW4dUjb/wRY9ZIsrG t1Sqk1HlaBL/1aCJCeidiOGQ+qQtanQrw0xQDyImFj+qIzV+JOzSFHvqrJP3+gsgwN0Y vvW7I9ve7EEE9CfATLwPQFhPClEKMQkeCYpzYVmocivQdKfkcjNHnMGXeiBVpPHy+7aq 5XvGLoRjuED4yftzjEwYb9nrFTHoubIgnDj3heH3rASHMilvGeHnD1RAQdvsuZl+p78w ixfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=NeQpk86S0vBOYYtLpIAqK8kTWLQJ7iK7jzELiikKnw4=; b=NwNiNwBDP1BjJdG+JnxRxGFISe8e6t3X5X1geL0EcpaheJG6st7lgHYNf71vKdIkRQ 1n3iBQDwZU2SVX/Wi/pOiYjkAHIppJmAbJBcEPqzobYRxQLBlnJQCTBtpTLouxAh3dQ8 11BI+ln1xrbMlO3lqvkSJwSfsGRYSoxMGXhKmGlIRcObDT5myuK2T848TrrxtHJl7Nji qEKmttUsEgSCRjHxtdru8vsBKFSRi54VGRg3i1nx05/Lb5jBwEI0raO5hi4L+CFhg1wA rD5WGsyphXhhReP0ktlLID1uEHS0OaBjbAQKAOePg4ZTGNZCp4RuVw5McM2Ot+E9PpLd Ih2w== X-Gm-Message-State: AElRT7GcTJK18f1B4r0vBFwc9GC1rDIRobEUynUifN/kLahWKwrznQly H0JbjKwc+fZU6TLgK2yus2PQdwlJttPJRShbNB1KWcbx X-Received: by 10.46.109.17 with SMTP id i17mr3131463ljc.115.1521024843669; Wed, 14 Mar 2018 03:54:03 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a19:a544:0:0:0:0:0 with HTTP; Wed, 14 Mar 2018 03:53:43 -0700 (PDT) In-Reply-To: <20180314003655.12141-2-djkurtz@chromium.org> References: <20180314003655.12141-1-djkurtz@chromium.org> <20180314003655.12141-2-djkurtz@chromium.org> From: Ricardo Ribalda Delgado Date: Wed, 14 Mar 2018 11:53:43 +0100 Message-ID: Subject: Re: [PATCH 1/3] serial: 8250_early: Add earlycon support for AMD Carrizo / Stoneyridge To: Daniel Kurtz Cc: adurbin@chromium.org, Greg Kroah-Hartman , Jiri Slaby , Marc Gonzalez , Douglas Anderson , Matt Redfearn , Jeffy Chen , "open list:SERIAL DRIVERS" , open list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Daniel On Wed, Mar 14, 2018 at 1:36 AM, Daniel Kurtz wrote: > > AMD Carrizo / Stoneyridge use a DesignWare 8250 UART that uses a 48 MHz > input clock. > > Allow these platforms to set up this clock by specifying a kernel command > line like: > earlycon=amdcz,mmio32,0xfedc6000,115200 If the port and the mode (mmio32) is always fixed, couldn't we just add those two into early_amdcz_setup? Thanks!