Received: by 10.213.65.68 with SMTP id h4csp917933imn; Wed, 14 Mar 2018 04:17:07 -0700 (PDT) X-Google-Smtp-Source: AG47ELsJsjlOnCZfJQHnV6gY7t1/BJ5ZA5b9ppNhHtSQfw45fp0tYZcurFusMX0KQr5GJ/nmYYPr X-Received: by 2002:a17:902:8b82:: with SMTP id ay2-v6mr3690271plb.12.1521026227661; Wed, 14 Mar 2018 04:17:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521026227; cv=none; d=google.com; s=arc-20160816; b=FEjgtnK0Q1mDEV7ZTZeb9Hv9gVNaXtocvZrkBifL16qP9oyDDU6p8zeRS8wXe8+5pw NC5LjLPLnkAkkK4ur8/Z2IBr6jN+c6rDg6awWrXmIYXoLWmf2aYN4e/LAIlrFflykD1A rWxOI3NdCXuOt2dgxQELWFiDVGxPs1jSwUCLAIg6JGPIniA77z2HGaxJZkUr7QU1M1a2 dI35xALg8MMAXNskO77MzeiL0leEvBpa4nymM/XCTtq06jHjoCUlFQ7EXNyhd7unUWRK h00WCm+jRPE6eXEC/v16f2gDgCy882ItmScjowmU1L5GLqYI50GQXOwoojB8/YIZSY9y 08Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:organization:from:references:cc:to:subject :arc-authentication-results; bh=ovhrdjbhtfFwawZBg98c/abei+yOrqv66CTf1nPvOuQ=; b=wczxYUBPgqhXNSBhjovSdyTvRxwqEDyALjyA+edGhvEFfa6xzLQ0SYfQ9iEbpquBFB 6X2RE4F9+P82+uIyAZGqMMUhBh5sesHh07c1ml/ynbdaiPcyyE3C60QNjgcp4kSPzGkP sNlqOWMwbNSFyrGHPSsmwZWGLOo5C563pwN/xRcS5EcYioTobXYExEPQWL0KHN9t9AWh /EK/hdeArzJKP057aRi01SRXiOFo8q4K1Wxz/BADizwjCQoy0MJ3MqHDgTl9Ru56+fXq XK82BRFuWZ9DuRLZtucu2WE/MPbjax7dH7RkF0YhE7K1eI3OQGyjCdsbA9gBdbDqlyLm yoRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p3si1888940pfh.84.2018.03.14.04.16.51; Wed, 14 Mar 2018 04:17:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751508AbeCNLPx (ORCPT + 99 others); Wed, 14 Mar 2018 07:15:53 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:50890 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751289AbeCNLPv (ORCPT ); Wed, 14 Mar 2018 07:15:51 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9929715AB; Wed, 14 Mar 2018 04:15:51 -0700 (PDT) Received: from [10.1.207.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F40A13F487; Wed, 14 Mar 2018 04:15:48 -0700 (PDT) Subject: Re: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available To: Matt Redfearn , Ralf Baechle , Thomas Gleixner Cc: linux-mips@linux-mips.org, Jason Cooper , Dengcheng Zhu , linux-kernel@vger.kernel.org, Philippe Ombredanne , Paul Burton , Kate Stewart , Greg Kroah-Hartman References: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> From: Marc Zyngier Organization: ARM Ltd Message-ID: Date: Wed, 14 Mar 2018 11:15:47 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Matt, On 05/01/18 10:31, Matt Redfearn wrote: > > This series enables the MIPS GIC driver to make use of the EIC mode > supported in some MIPS cores. In this mode, the cores 6 interrupt lines > are switched to represent a vector number, 0..63. Currently all GIC > interrupts are routed to a single CPU interrupt pin, but this is > inefficient since we end up checking both local and shared interrupt > flag registers for both local and shared interrupts. This introduces > additional latency into the interrupt paths. With EIC mode this can be > improved by using separate vectors for local and shared interrupts. > > This series is based on 4.15-rc6 and has been tested on Boston, Malta & > SEAD3 MIPS platforms implementing a GIC with and without EIC mode > supported in hardware. What the status of this series? Thanks, M. -- Jazz is not dead. It just smells funny...