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[209.132.180.67]) by mx.google.com with ESMTP id g9-v6si2113647plk.644.2018.03.14.08.55.43; Wed, 14 Mar 2018 08:56:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751857AbeCNPxz (ORCPT + 99 others); Wed, 14 Mar 2018 11:53:55 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:54554 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752006AbeCNPxw (ORCPT ); Wed, 14 Mar 2018 11:53:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5092F1596; Wed, 14 Mar 2018 08:53:52 -0700 (PDT) Received: from [10.1.207.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C9F3F3F53D; Wed, 14 Mar 2018 08:53:47 -0700 (PDT) Subject: Re: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available To: James Hogan Cc: Matt Redfearn , Ralf Baechle , Thomas Gleixner , linux-mips@linux-mips.org, Jason Cooper , Dengcheng Zhu , linux-kernel@vger.kernel.org, Philippe Ombredanne , Paul Burton , Kate Stewart , Greg Kroah-Hartman References: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com> <20180314154641.GA8976@saruman> From: Marc Zyngier Organization: ARM Ltd Message-ID: Date: Wed, 14 Mar 2018 15:53:45 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180314154641.GA8976@saruman> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/03/18 15:46, James Hogan wrote: > On Wed, Mar 14, 2018 at 11:15:47AM +0000, Marc Zyngier wrote: >> Hi Matt, >> >> On 05/01/18 10:31, Matt Redfearn wrote: >>> >>> This series enables the MIPS GIC driver to make use of the EIC >>> mode supported in some MIPS cores. In this mode, the cores 6 >>> interrupt lines are switched to represent a vector number, >>> 0..63. Currently all GIC interrupts are routed to a single CPU >>> interrupt pin, but this is inefficient since we end up checking >>> both local and shared interrupt flag registers for both local >>> and shared interrupts. This introduces additional latency into >>> the interrupt paths. With EIC mode this can be improved by >>> using separate vectors for local and shared interrupts. >>> >>> This series is based on 4.15-rc6 and has been tested on Boston, >>> Malta & SEAD3 MIPS platforms implementing a GIC with and >>> without EIC mode supported in hardware. >> >> What the status of this series? > > FYI I've been meaning to test it with KVM, since host EIC I think > will affect KVM & guest stuff. OK. I'll park that until I hear from you guys. Thanks, M. -- Jazz is not dead. It just smells funny...