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[209.132.180.67]) by mx.google.com with ESMTP id k6si2439991pgp.709.2018.03.14.14.47.10; Wed, 14 Mar 2018 14:47:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=ctV7GMFb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751889AbeCNVo5 (ORCPT + 99 others); Wed, 14 Mar 2018 17:44:57 -0400 Received: from mail-ot0-f195.google.com ([74.125.82.195]:44918 "EHLO mail-ot0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751447AbeCNVoy (ORCPT ); Wed, 14 Mar 2018 17:44:54 -0400 Received: by mail-ot0-f195.google.com with SMTP id 79-v6so4803028oth.11 for ; Wed, 14 Mar 2018 14:44:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xn3xab9TZitVtgpX2B6oBTQHFMNCHW2aw3FmWgVGJ0w=; b=ctV7GMFbxZEVB1wSK/6Sl1DVYI+NZQ6k7cB19Op+5hhKwpx+H1vCJxsYbIhq/BG/9X oduhKwwbDdfMJ/jNR0qO8ULM5LzvJeo9A9hRw1cRwYrT7ySePT1zeT52jTEYAQwvQVS0 w55iT3vJHkN/lil50DCvfbrDIleehh+AJMgk4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xn3xab9TZitVtgpX2B6oBTQHFMNCHW2aw3FmWgVGJ0w=; b=CKwhT1za+9faH7EnR/CmE+YsAqYpIke+Y1w3PiSxYofzHUxa3AowYmrcJfC+wiYObO eaEvLH9++VU2YkkAiJ2iO1mD+73RtPPePxrHGkI8wwqo1Fr4zXb5hUM1GAceZsvHaef3 sjUKdkxXOezlITi8hgOYJoe9TTPW5qJCWKQcOS05bVCe6WU/LSQeuGBsN+1ITn12MYdq QkjCp9hF9TaAWShSZZvdz/WlwilmK/0Z+DLc/7TEAf5jUjVkLiN8mUiNlg75m7TUM7Yk zU39ZYy6uWbq7hNpRxG4uO54SuI6i2GbfYpZor7QdDICA75VFFuXpuPHxMVTDyExJoZl 091g== X-Gm-Message-State: AElRT7GXU73XThDhC3lZwgnL2mPNvh4PQjQw4FQchLUOJatPScFA7YzB LnjmEhJ5wE5Caps351HAUWLyJQ== X-Received: by 10.157.112.3 with SMTP id k3mr4179595otj.189.1521063893752; Wed, 14 Mar 2018 14:44:53 -0700 (PDT) Received: from djkurtz2.bld.corp.google.com ([2620:15c:183:0:1cfd:61a5:7215:5f9c]) by smtp.gmail.com with ESMTPSA id p200sm1974922oic.0.2018.03.14.14.44.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Mar 2018 14:44:53 -0700 (PDT) From: Daniel Kurtz To: Greg Kroah-Hartman Cc: adurbin@chromium.org, linux-kernel@vger.kernel.org, Daniel Kurtz , Jiri Slaby , Douglas Anderson , Matt Redfearn , Marc Gonzalez , Jeffy Chen , linux-serial@vger.kernel.org (open list:SERIAL DRIVERS) Subject: [PATCH v2 1/3] serial: 8250_early: Add earlycon support for AMD Carrizo / Stoneyridge Date: Wed, 14 Mar 2018 15:44:36 -0600 Message-Id: <20180314214439.27806-2-djkurtz@chromium.org> X-Mailer: git-send-email 2.16.2.804.g6dcf76e118-goog In-Reply-To: <20180314214439.27806-1-djkurtz@chromium.org> References: <20180314214439.27806-1-djkurtz@chromium.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD Carrizo / Stoneyridge use a DesignWare 8250 UART that uses a 48 MHz input clock. Allow these platforms to set up this clock by specifying a kernel command line like: earlycon=amdcz,mmio32,0xfedc6000,115200 Signed-off-by: Daniel Kurtz Suggested-by: Andy Shevchenko Reviewed-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_early.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index ae6a256524d8..c6bf971a6038 100644 --- a/drivers/tty/serial/8250/8250_early.c +++ b/drivers/tty/serial/8250/8250_early.c @@ -195,3 +195,18 @@ static int __init early_au_setup(struct earlycon_device *dev, const char *opt) OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup); #endif + +#ifdef CONFIG_SERIAL_8250_DW +static int __init early_amdcz_setup(struct earlycon_device *dev, + const char *opt) +{ + struct uart_port *port = &dev->port; + + port->uartclk = 48000000; + + return early_serial8250_setup(dev, opt); +} + +EARLYCON_DECLARE(amdcz, early_amdcz_setup); + +#endif -- 2.16.2.804.g6dcf76e118-goog