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[209.132.180.67]) by mx.google.com with ESMTP id g16si2755402pgn.813.2018.03.14.19.07.40; Wed, 14 Mar 2018 19:07:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=L6k8k0e8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751788AbeCOCEy (ORCPT + 99 others); Wed, 14 Mar 2018 22:04:54 -0400 Received: from mail-ot0-f195.google.com ([74.125.82.195]:35282 "EHLO mail-ot0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751696AbeCOCEv (ORCPT ); Wed, 14 Mar 2018 22:04:51 -0400 Received: by mail-ot0-f195.google.com with SMTP id r30-v6so5373604otr.2 for ; Wed, 14 Mar 2018 19:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aKVFpScwnQ8pzQB6DZDzG4ua3jf7n8aw9buIr62C8V0=; b=L6k8k0e8sraom9J0y1jNeYfkfcEG1/YEFeSIw+tSOAooK0chBGiO/tBoA4tjFTw29k T9OsCSr4XrxNweHPJuGLk5C08LvKUQ1zo7VNDyad4/ezD0szDbBfdpPfJsfakWxWLPvI xpcITYkqxWbRPUw+1f4hm51lazGVvFZZesHag= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aKVFpScwnQ8pzQB6DZDzG4ua3jf7n8aw9buIr62C8V0=; b=qql+J0ll21aKD8+odjXoZIRXPEDwv8fxue3DxlWpO120ncH4NMQBu7rYOpBaQIdBtP uTpmSSQzz5FNfQRpwI/bZtcm5pzP+BA93IOdpD25D4XEEjFmoorUMoGkIlo2R8kv+yHn VQw1MXYVoTLDLLSJn90Yne+ltLZ8kDghDA9JT+U74EdKA/KXJO2p6WC7C2VfB6u5n0um 6qRE0ZgPZEmJnZOt6IbMNfcXRk49/nXk1ZjiXhHi6AZZh9USx4is7k9f8vKsXESpAe1Q xL5Lx1MaB+k3HhhD5PUAp2zoIAR4UqEsgwNP7j/ueWkqGIEzhBDlbvL/VeJiUAbvZru6 WbNw== X-Gm-Message-State: AElRT7GW7hcV/IQHJ30PcxJ9RDuu/2Bgf5Nwgk2ZuBW2QrqJKEAoUkBW UObWkOOpv7MW7lsxkl4Hm3sJkw== X-Received: by 10.157.58.53 with SMTP id j50mr4252058otc.157.1521079490917; Wed, 14 Mar 2018 19:04:50 -0700 (PDT) Received: from djkurtz2.bld.corp.google.com ([2620:15c:183:0:1cfd:61a5:7215:5f9c]) by smtp.gmail.com with ESMTPSA id j142sm1642773oih.7.2018.03.14.19.04.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Mar 2018 19:04:50 -0700 (PDT) From: Daniel Kurtz To: Greg Kroah-Hartman Cc: adurbin@chromium.org, linux-kernel@vger.kernel.org, Daniel Kurtz , Jiri Slaby , Marc Gonzalez , Jeffy Chen , Douglas Anderson , Matt Redfearn , linux-serial@vger.kernel.org (open list:SERIAL DRIVERS) Subject: [PATCH v3 1/3] serial: 8250_early: Add earlycon support for AMD Carrizo / Stoneyridge Date: Wed, 14 Mar 2018 20:04:43 -0600 Message-Id: <20180315020445.150604-2-djkurtz@chromium.org> X-Mailer: git-send-email 2.16.2.804.g6dcf76e118-goog In-Reply-To: <20180315020445.150604-1-djkurtz@chromium.org> References: <20180315020445.150604-1-djkurtz@chromium.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD Carrizo / Stoneyridge use a DesignWare 8250 UART that uses a 48 MHz input clock. Allow these platforms to set up this clock by specifying a kernel command line like: earlycon=amdcz,mmio32,0xfedc6000,115200 Signed-off-by: Daniel Kurtz Suggested-by: Andy Shevchenko Reviewed-by: Andy Shevchenko --- Changes since v1: * added Reviewed-by & Suggested-by drivers/tty/serial/8250/8250_early.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index ae6a256524d8..c6bf971a6038 100644 --- a/drivers/tty/serial/8250/8250_early.c +++ b/drivers/tty/serial/8250/8250_early.c @@ -195,3 +195,18 @@ static int __init early_au_setup(struct earlycon_device *dev, const char *opt) OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup); #endif + +#ifdef CONFIG_SERIAL_8250_DW +static int __init early_amdcz_setup(struct earlycon_device *dev, + const char *opt) +{ + struct uart_port *port = &dev->port; + + port->uartclk = 48000000; + + return early_serial8250_setup(dev, opt); +} + +EARLYCON_DECLARE(amdcz, early_amdcz_setup); + +#endif -- 2.16.2.804.g6dcf76e118-goog