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Date:   Thu, 15 Mar 2018 01:01:32 -0300
From:   Henrique de Moraes Holschuh <hmh@hmh.eng.br>
To:     Borislav Petkov <bp@alien8.de>
Cc:     X86 ML <x86@kernel.org>, Emanuel Czirai <xftroxgpx@protonmail.com>,
        Ashok Raj <ashok.raj@intel.com>,
        Tom Lendacky <thomas.lendacky@amd.com>,
        LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] x86/microcode: Fix CPU synchronization routine
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On Thu, 15 Mar 2018, Borislav Petkov wrote:
> On Wed, Mar 14, 2018 at 10:00:14PM -0300, Henrique de Moraes Holschuh wrote:
> > Intel takes anything from twenty thousand cycles to several *million*
> > cycles per core, proportional to microcode update size.
> 
> Got any hard data to back that claim up?

A reasonably well-known paper on intel microcode updates[1] profiled
that very well, years ago (2013).  The information about a linear
increase in update time versus update size comes from that paper (I did
not attempt to reproduce his findings, though).

When I measured my Xeon X5550 workstation doing an early update, the
Xeon took about 1M cycles for the BSP, and 800k cycles for the APs (see
below).

To measure that, as far as I recall I just did a rdtsc right before the
wrmsr, and another right after, and stashed the result somewhere to be
able to print it out later in the BSP's case.  I repeated the process
(by rebooting) a few times.  There was a *lot* of variation, but not
enough to get it wrong by an order of magnitude.

I am surprised that this would be news to you, though.  It is not like I
have been quiet about how expensive these updates are on Intel over the
past years every time I sent you a patch related to this...

Anyway, here's my measurement data from 2013:

Xeon X5550:
microcode_early: CPU0: entire core updated early to revision 0x19, in 1016168 cycles
microcode_early: CPU1: entire core updated early to revision 0x19, in 842264 cycles
microcode_early: CPU2: entire core updated early to revision 0x19, in 846784 cycles
microcode_early: CPU3: entire core updated early to revision 0x19, in 838196 cycles


[1] HAWKES, Ben. "Notes on Intel Microcode Updates", March 2013.

-- 
  Henrique Holschuh