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[209.132.180.67]) by mx.google.com with ESMTP id p18si647475pfk.396.2018.03.15.01.17.47; Thu, 15 Mar 2018 01:18:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=lo6Xu65x; dkim=pass header.i=@codeaurora.org header.s=default header.b=QVgSGNkC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751617AbeCOIQp (ORCPT + 99 others); Thu, 15 Mar 2018 04:16:45 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57664 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750726AbeCOIQl (ORCPT ); Thu, 15 Mar 2018 04:16:41 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9D49360590; Thu, 15 Mar 2018 08:16:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521101800; bh=NtxmEPYr5xJCtQcP0ToDyGOV1vbRwuBWiX3qAWKmF1g=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=lo6Xu65xwBguEKa437YOuLmExe8n4nWHvqOcPl5vKbyu7pIE+TeEK+LfuQrb7GNRy 2X0XtpDymEvueakHHiMEEugiofIXy3na8EPT/jPqS8oWzunSg1fszbd+HVc1Arg/i1 yAtoBf7CvbXFgzSigZraWATPGjWSMfNCsohBk28k= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from [10.206.25.65] (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7D02860390; Thu, 15 Mar 2018 08:16:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521101799; bh=NtxmEPYr5xJCtQcP0ToDyGOV1vbRwuBWiX3qAWKmF1g=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=QVgSGNkCWWXm/TLThWT1Ob2sCms/jv6WO4Uqtzh4WVV/ZtHI7UVg8z00+WnnzJk3F BPgldHxI/svtjrc8yfqI4DJPyk3YWj9M4DH+GBBXR1No8qZVEKFqqPMavLbYHAMHZT Io9xcuDwEg1fu1N034QcpLCCFtinugWvBxPYkdVE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7D02860390 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org Subject: Re: [PATCH v1 2/2] usb: dwc3: Add Qualcomm DWC3 glue driver To: Felipe Balbi , Rob Herring , Andy Gross , Heikki Krogerus Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Greg Kroah-Hartman , open list References: <1520937362-28777-1-git-send-email-mgautam@codeaurora.org> <1520937362-28777-2-git-send-email-mgautam@codeaurora.org> <878taw8c81.fsf@linux.intel.com> <5a65d202-bb94-0f73-f9aa-9055a1cddf76@codeaurora.org> <87woyfrqgr.fsf@linux.intel.com> From: Manu Gautam Message-ID: <78b262e9-5682-0a56-3589-b5736fec10bc@codeaurora.org> Date: Thu, 15 Mar 2018 13:46:35 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <87woyfrqgr.fsf@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 3/14/2018 2:20 PM, Felipe Balbi wrote: > Hi, > > Manu Gautam writes: > [snip] >>>> - Support to replace pip3 clock going to DWC3 with utmi clock >>>> for hardware configuration where SSPHY is not used with DWC3. >>> Is that SW configurable? Really? In any case seems like this and SESSVLD >>> valid should be handled using Hans' and Heikki's mux support. >> Yes, with this we can use dwc3 without using SSPHY. Please point me to >> those patches. There are only bunch of register writes in glue wrapper to >> achieve the same. > https://www.spinics.net/lists/linux-usb/msg160868.html I looked at the patchset and thinking that adding mux for this may not be of much help here. Qscratch is part of dwc3 wrapper and uses same clock domain for its registers. Hence, I can't have a separate mux driver for same. Will have to register mux controller from this driver for these and use only in this driver as I dont expect any other client for same. So, can I proceed with existing logic? > >>>> +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom) >>>> +{ >>>> + struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); >>> nope! Glue shouldn't touch dwc3 at all. >> Other than PHY handles, need this to fail runtime suspend if dwc3 hasn't >> probed yet. > Will that even happen? You should pm_runtime_forbid() by default, > anyway and expect it to be enabled via sysfs later, no? It happens if I enable runtime_pm from probe which is the case right now. I will disable it from probe as you suggested. In any case dwc3 uses pm_runtime_forbid and expects it to be enabled from sysfs, so I dont get any benefit of enabling it from glue driver probe. Other than this, I need to access 'dwc->xhci' to resume root hub on remote wakeup. That I missed to mention earlier. > >>>> + dwc3_qcom_suspend_hsphy(qcom); >>>> + >>>> + if (dwc->usb2_generic_phy) >>>> + phy_pm_runtime_put_sync(dwc->usb2_generic_phy); >>>> + if (dwc->usb3_generic_phy) >>>> + phy_pm_runtime_put_sync(dwc->usb3_generic_phy); >>> core.c should do this. >> Recommended sequence from h/w programming guide is that: >> 1. PHY autosuspend must be left disabled - snps,dis_u2_susphy_quirk/dis_enblslpm_quirk >> 2. During runtime-suspend (say on xhci bus_suspend) , PHY should be suspended >>     using GUSB2PHYCFG register > this is something that dwc3 core can do on its own suspend implementation. > >> 3. Wait until pwr_event_irq_stat in qscratch reflects PHY transition to L2. > this is interesting part. Is this register accessible by the PHY driver? > Seems like that would be the best place to stuff this... This register is in controller wrapper which PHY driver can't access. Also clock domain is different. > >> 3. USB2 PHY driver can suspend - enable wakeup events and turns off clocks etc. > ... together with this. > >> 4. dwc3 glue driver can suspend. >> >> Since, pwr_event_irq stat can't be checked in core driver, I added this handling >> in glue driver. Alternative approach I can think of is to let dwc3 core suspend >> PHY using GUSBPHYCFG register on suspend,  add some delay before >> suspending PHY. Glue driver can check for pwr_event_irq stat and throw a >> warning if PHY not in L2. > almost :-) core_suspend fiddles with GUSB2PHYCFG for suspend and calls > phy_suspend() (or whatever the function is called heh), that will go to > your phy driver's suspend callback, which checks pwr_event_irq_stat and > then pm_runtime_put() to schedule ->runtime_suspend() so that can enable > wakeups and switch off clocks. Since phy driver can not access pwr_event_irq_stat, should I just use some delay and assume PHY gets suspended? > >>>> + irq = platform_get_irq_byname(pdev, "dp_hs_phy_irq"); >>>> + if (irq > 0) { >>>> + irq_set_status_flags(irq, IRQ_NOAUTOEN); >>> why do you need to set this flag? >> These wakeup_irqs should be enabled only during suspend. With this flag I >> don't need to disable irq immediately after requesting it. > oh, okay. You may want to add a comment here :-) Sure. -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project