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[209.132.180.67]) by mx.google.com with ESMTP id t192si4491589pgb.595.2018.03.15.20.30.31; Thu, 15 Mar 2018 20:30:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=k4SaEXBq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933361AbeCPC7F (ORCPT + 99 others); Thu, 15 Mar 2018 22:59:05 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:33995 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751791AbeCPC7B (ORCPT ); Thu, 15 Mar 2018 22:59:01 -0400 Received: by mail-pl0-f67.google.com with SMTP id u11-v6so1422349plq.1 for ; Thu, 15 Mar 2018 19:59:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=WgX7MRw2lL/HqVI4NjkAY3pTLJ9IMNgmqnUFv1MFNjo=; b=k4SaEXBq4RJS2GfbY+EHCYR7fctUzNCyqDtDxMVsfsB+t+NC2+/0FFks1xDGOjTn51 H6eVppwkouoBxHgb8hLcUjMZZvgXR3hc4QmzroxBmk7p5AEPHPxtsRXF01Jpg//+5JZx 9xelB1boOkXSYuha9lur2qLZfYbpEFOcr3WPM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WgX7MRw2lL/HqVI4NjkAY3pTLJ9IMNgmqnUFv1MFNjo=; b=NUHl47KpNREfQGRlMwb6GaY5qBNRf2wb4Xx0Q/3y41W/tg2Vhk4nlOF/eB7Lc1+MXd Zo4aVtG1U+/K/YkZQQMHNzO/mZMlH0hocpnbVuBgB3//AdGDngpCtCfVTluC6E6Boa6w B2HsIMM7MNwEsrZ0FU1izb/XqChuhAfZ4oVkp+ScV+zk27XH/WdR7acr6L/X1HcjIlRG 0vEN2Zea9EIhcehcshBplgMwUbK2+3On9Yv4DE5bVdbI6HibCizmtEP51Wc+eb/TSC7b xLork03SXL3kYGMKtEVO6c5kvCpxOK5Jcvta6llPvsRy2vSyMy+rEOrQk+IPlNpEN5aW DvyQ== X-Gm-Message-State: AElRT7HRLJYXlkWGr0xG+73/Fj1O9v2CpiKqDRgR9pzRqQYEkQ0j12Zc LuVtplT85AJTdpJO6aDcEkbOAQ== X-Received: by 2002:a17:902:968c:: with SMTP id n12-v6mr220792plp.371.1521169141307; Thu, 15 Mar 2018 19:59:01 -0700 (PDT) Received: from amstan-desktop.mtv.corp.google.com ([2620:0:1000:1501:fc25:2d9b:94b3:3540]) by smtp.gmail.com with ESMTPSA id y3sm10736554pgc.81.2018.03.15.19.58.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 19:59:00 -0700 (PDT) From: Alexandru M Stan To: David Airlie , Rob Herring , Mark Rutland , Archit Taneja , Andrzej Hajda , Laurent Pinchart , Sean Paul Cc: devicetree@vger.kernel.org, Enric Balletbo i Serra , Heiko Stuebner , briannorris@chromium.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, marcheu@chromium.org, hoegsberg@chromium.org, Thierry Escande , Jeffy Chen , Alexandru M Stan , Yakir Yang , Daniel Vetter , zain wang , Sylwester Nawrocki , Marek Szyprowski Subject: [PATCH 0/2] Add backlight-pwm-passthru in analogix DP driver Date: Thu, 15 Mar 2018 19:56:57 -0700 Message-Id: <20180316025659.217423-1-amstan@chromium.org> X-Mailer: git-send-email 2.13.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I noticed that the backlight on the ASUS Chromebook Flip C101 (bob) is flickering. We're sending it a high frequency pwm signal, but the EDP panel decided to "parse" the signal, read the duty cycle, then make its own signal that it sends to the LEDs. So even though we send a nice high refresh rate at 1200Hz, the panel backlight flickers at 200Hz (which is not even divisible by the 60Hz refresh rate). The fix for that is to enable the EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU bit from the DPCD EDP registers. This makes the panel actually follow the signal we're giving it. This series includes the optional dt binding to enable this fix (backlight-pwm-passthru) and the corresponding code in the analogix drm/bridge driver. Alexandru M Stan (2): dt-bindings: analogix-dp: Add backlight-pwm-passthru drm/bridge: analogix: Enable EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU .../bindings/display/bridge/analogix_dp.txt | 4 ++ drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 48 ++++++++++++++++++++++ drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 1 + 3 files changed, 53 insertions(+) -- 2.13.5